diff options
Diffstat (limited to 'src/southbridge/amd/cimx/sb800/cfg.c')
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/cfg.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 57ff7181af..45a460be4f 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -50,6 +50,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; + sb_config->BuildParameters.SioHwmBaseAddress = SIO_HWM_BASE_ADDRESS; sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; sb_config->BuildParameters.GecShadowRomBase = GEC_BASE_ADDRESS; sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; @@ -94,6 +95,10 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_SDIN_PIN; sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL; + /* LPC */ + /* SuperIO hardware monitor register access */ + sb_config->SioHwmPortEnable = CONFIG_SB_SUPERIO_HWM; + /* * GPP. default configure only enable port0 with 4 lanes, * configure in devicetree.cb would overwrite the default configuration |