diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/alderlake/bootblock/report_platform.c | 12 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 14 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/chipset_pch_s.cb | 30 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/cpu.c | 17 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 8 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/cpu.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/vr_config.c | 32 | ||||
| -rw-r--r-- | src/soc/intel/common/block/graphics/graphics.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/systemagent/systemagent.c | 8 |
9 files changed, 126 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index d360197555..01be2aad50 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -75,6 +75,14 @@ static struct { { PCI_DID_INTEL_ADL_S_ID_12, "Alderlake-S (2+0)" }, { PCI_DID_INTEL_ADL_S_ID_13, "Alderlake-S" }, { PCI_DID_INTEL_ADL_S_ID_14, "Alderlake-S" }, + { PCI_DID_INTEL_RPL_HX_ID_1, "Raptorlake-HX (8+16)" }, + { PCI_DID_INTEL_RPL_HX_ID_2, "Raptorlake-HX (8+12)" }, + { PCI_DID_INTEL_RPL_HX_ID_3, "Raptorlake-HX (8+8)" }, + { PCI_DID_INTEL_RPL_HX_ID_4, "Raptorlake-HX (6+8)" }, + { PCI_DID_INTEL_RPL_HX_ID_5, "Raptorlake-HX (6+4)" }, + { PCI_DID_INTEL_RPL_HX_ID_6, "Raptorlake-HX (8+8)" }, + { PCI_DID_INTEL_RPL_HX_ID_7, "Raptorlake-HX (6+8)" }, + { PCI_DID_INTEL_RPL_HX_ID_8, "Raptorlake-HX (6+4)" }, { PCI_DID_INTEL_RPL_P_ID_1, "Raptorlake-P" }, { PCI_DID_INTEL_RPL_P_ID_2, "Raptorlake-P" }, { PCI_DID_INTEL_RPL_P_ID_3, "Raptorlake-P" }, @@ -207,6 +215,10 @@ static struct { { PCI_DID_INTEL_ADL_S_GT2, "Alderlake S GT2" }, { PCI_DID_INTEL_ADL_S_GT2_1, "Alderlake S GT2" }, { PCI_DID_INTEL_ADL_S_GT2_2, "Alderlake S GT2" }, + { PCI_DID_INTEL_RPL_HX_GT1, "Raptorlake HX GT1" }, + { PCI_DID_INTEL_RPL_HX_GT2, "Raptorlake HX GT2" }, + { PCI_DID_INTEL_RPL_HX_GT3, "Raptorlake HX GT3" }, + { PCI_DID_INTEL_RPL_HX_GT4, "Raptorlake HX GT4" }, { PCI_DID_INTEL_RPL_P_GT1, "Raptorlake P GT1" }, { PCI_DID_INTEL_RPL_P_GT2, "Raptorlake P GT2" }, { PCI_DID_INTEL_RPL_P_GT3, "Raptorlake P GT3" }, diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index df978a99e6..16f1390a89 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -95,6 +95,11 @@ enum soc_intel_alderlake_power_limits { RPL_S_201_35W_CORE, RPL_S_201_46W_CORE, RPL_S_201_65W_CORE, + RPL_HX_8_16_55W_CORE, + RPL_HX_8_12_55W_CORE, + RPL_HX_8_8_55W_CORE, + RPL_HX_6_8_55W_CORE, + RPL_HX_6_4_55W_CORE, ADL_POWER_LIMITS_COUNT }; @@ -109,6 +114,7 @@ enum soc_intel_alderlake_cpu_tdps { TDP_35W = 35, TDP_45W = 45, TDP_46W = 46, + TDP_55W = 55, TDP_58W = 58, TDP_60W = 60, TDP_65W = 65, @@ -188,6 +194,14 @@ static const struct { { PCI_DID_INTEL_ADL_S_ID_12, RPL_S_201_35W_CORE, TDP_35W }, { PCI_DID_INTEL_ADL_S_ID_12, RPL_S_201_46W_CORE, TDP_46W }, { PCI_DID_INTEL_ADL_S_ID_12, RPL_S_201_65W_CORE, TDP_65W }, + { PCI_DID_INTEL_RPL_HX_ID_1, RPL_HX_8_16_55W_CORE, TDP_55W }, + { PCI_DID_INTEL_RPL_HX_ID_2, RPL_HX_8_12_55W_CORE, TDP_55W }, + { PCI_DID_INTEL_RPL_HX_ID_3, RPL_HX_8_8_55W_CORE, TDP_55W }, + { PCI_DID_INTEL_RPL_HX_ID_4, RPL_HX_6_8_55W_CORE, TDP_55W }, + { PCI_DID_INTEL_RPL_HX_ID_5, RPL_HX_6_4_55W_CORE, TDP_55W }, + { PCI_DID_INTEL_RPL_HX_ID_6, RPL_HX_8_8_55W_CORE, TDP_55W }, + { PCI_DID_INTEL_RPL_HX_ID_7, RPL_HX_6_8_55W_CORE, TDP_55W }, + { PCI_DID_INTEL_RPL_HX_ID_8, RPL_HX_6_4_55W_CORE, TDP_55W }, }; /* Types of display ports */ diff --git a/src/soc/intel/alderlake/chipset_pch_s.cb b/src/soc/intel/alderlake/chipset_pch_s.cb index b2719a850c..6bcfab1f45 100644 --- a/src/soc/intel/alderlake/chipset_pch_s.cb +++ b/src/soc/intel/alderlake/chipset_pch_s.cb @@ -92,6 +92,36 @@ chip soc/intel/alderlake .tdp_pl4 = 44, }" + register "power_limits_config[RPL_HX_8_16_55W_CORE]" = "{ + .tdp_pl1_override = 55, + .tdp_pl2_override = 157, + .tdp_pl4 = 246, + }" + + register "power_limits_config[RPL_HX_8_12_55W_CORE]" = "{ + .tdp_pl1_override = 55, + .tdp_pl2_override = 157, + .tdp_pl4 = 246, + }" + + register "power_limits_config[RPL_HX_8_8_55W_CORE]" = "{ + .tdp_pl1_override = 55, + .tdp_pl2_override = 157, + .tdp_pl4 = 246, + }" + + register "power_limits_config[RPL_HX_6_8_55W_CORE]" = "{ + .tdp_pl1_override = 55, + .tdp_pl2_override = 130, + .tdp_pl4 = 200, + }" + + register "power_limits_config[RPL_HX_6_4_55W_CORE]" = "{ + .tdp_pl1_override = 55, + .tdp_pl2_override = 130, + .tdp_pl4 = 200, + }" + register "power_limits_config[RPL_S_8161_35W_CORE]" = "{ .tdp_pl1_override = 35, .tdp_pl2_override = 106, diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 2f5deea208..fafd54d9f1 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -242,6 +242,17 @@ enum adl_cpu_type get_adl_cpu_type(void) PCI_DID_INTEL_ADL_N_ID_4, }; + const uint16_t rpl_hx_mch_ids[] = { + PCI_DID_INTEL_RPL_HX_ID_1, + PCI_DID_INTEL_RPL_HX_ID_2, + PCI_DID_INTEL_RPL_HX_ID_3, + PCI_DID_INTEL_RPL_HX_ID_4, + PCI_DID_INTEL_RPL_HX_ID_5, + PCI_DID_INTEL_RPL_HX_ID_6, + PCI_DID_INTEL_RPL_HX_ID_7, + PCI_DID_INTEL_RPL_HX_ID_8, + }; + const uint16_t rpl_s_mch_ids[] = { PCI_DID_INTEL_RPL_S_ID_1, PCI_DID_INTEL_RPL_S_ID_2, @@ -287,6 +298,11 @@ enum adl_cpu_type get_adl_cpu_type(void) return ADL_N; } + for (size_t i = 0; i < ARRAY_SIZE(rpl_hx_mch_ids); i++) { + if (rpl_hx_mch_ids[i] == mchid) + return RPL_HX; + } + for (size_t i = 0; i < ARRAY_SIZE(rpl_p_mch_ids); i++) { if (rpl_p_mch_ids[i] == mchid) return RPL_P; @@ -306,6 +322,7 @@ uint8_t get_supported_lpm_mask(void) return LPM_S0i2_0 | LPM_S0i3_0; case ADL_S: case RPL_S: + case RPL_HX: return LPM_S0i2_0 | LPM_S0i2_1; default: printk(BIOS_ERR, "Unknown ADL CPU type: %d\n", type); diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 657e089a63..13abd6f975 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -539,6 +539,14 @@ static uint16_t get_vccin_aux_imon_iccmax(void) case PCI_DID_INTEL_ADL_S_ID_10: case PCI_DID_INTEL_ADL_S_ID_11: case PCI_DID_INTEL_ADL_S_ID_12: + case PCI_DID_INTEL_RPL_HX_ID_1: + case PCI_DID_INTEL_RPL_HX_ID_2: + case PCI_DID_INTEL_RPL_HX_ID_3: + case PCI_DID_INTEL_RPL_HX_ID_4: + case PCI_DID_INTEL_RPL_HX_ID_5: + case PCI_DID_INTEL_RPL_HX_ID_6: + case PCI_DID_INTEL_RPL_HX_ID_7: + case PCI_DID_INTEL_RPL_HX_ID_8: return ICC_MAX_ADL_S; case PCI_DID_INTEL_RPL_S_ID_1: case PCI_DID_INTEL_RPL_S_ID_2: diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h index 581e6bdda5..d081e85a57 100644 --- a/src/soc/intel/alderlake/include/soc/cpu.h +++ b/src/soc/intel/alderlake/include/soc/cpu.h @@ -25,6 +25,7 @@ enum adl_cpu_type { ADL_N, ADL_P, ADL_S, + RPL_HX, RPL_P, RPL_S, }; diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index 23079833f7..a3083f5a1d 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -159,6 +159,14 @@ static const struct vr_lookup vr_config_ll[] = { { PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, { PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, { PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, + { PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, + { PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, + { PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, + { PCI_DID_INTEL_RPL_HX_ID_4, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, + { PCI_DID_INTEL_RPL_HX_ID_5, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, + { PCI_DID_INTEL_RPL_HX_ID_6, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, + { PCI_DID_INTEL_RPL_HX_ID_7, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, + { PCI_DID_INTEL_RPL_HX_ID_8, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, }; static const struct vr_lookup vr_config_icc[] = { @@ -210,6 +218,14 @@ static const struct vr_lookup vr_config_icc[] = { { PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_ICC(120, 30) }, { PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_ICC(140, 30) }, { PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_ICC(100, 30) }, + { PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_ICC(215, 30) }, + { PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_ICC(215, 30) }, + { PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_ICC(215, 30) }, + { PCI_DID_INTEL_RPL_HX_ID_4, 55, VR_CFG_ALL_DOMAINS_ICC(160, 30) }, + { PCI_DID_INTEL_RPL_HX_ID_5, 55, VR_CFG_ALL_DOMAINS_ICC(160, 30) }, + { PCI_DID_INTEL_RPL_HX_ID_6, 55, VR_CFG_ALL_DOMAINS_ICC(215, 30) }, + { PCI_DID_INTEL_RPL_HX_ID_7, 55, VR_CFG_ALL_DOMAINS_ICC(160, 30) }, + { PCI_DID_INTEL_RPL_HX_ID_8, 55, VR_CFG_ALL_DOMAINS_ICC(160, 30) }, }; static const struct vr_lookup vr_config_tdc_timewindow[] = { @@ -261,6 +277,14 @@ static const struct vr_lookup vr_config_tdc_timewindow[] = { { PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, + { PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, + { PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, + { PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, + { PCI_DID_INTEL_RPL_HX_ID_4, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, + { PCI_DID_INTEL_RPL_HX_ID_5, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, + { PCI_DID_INTEL_RPL_HX_ID_6, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, + { PCI_DID_INTEL_RPL_HX_ID_7, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, + { PCI_DID_INTEL_RPL_HX_ID_8, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, }; static const struct vr_lookup vr_config_tdc_currentlimit[] = { @@ -312,6 +336,14 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = { { PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(51, 22) }, { PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(69, 22) }, { PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(44, 22) }, + { PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, + { PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, + { PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, + { PCI_DID_INTEL_RPL_HX_ID_4, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, + { PCI_DID_INTEL_RPL_HX_ID_5, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, + { PCI_DID_INTEL_RPL_HX_ID_6, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, + { PCI_DID_INTEL_RPL_HX_ID_7, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, + { PCI_DID_INTEL_RPL_HX_ID_8, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, }; static void fill_vr_fast_vmode(FSP_S_CONFIG *s_cfg, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 012b18af44..9b48e1d850 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -316,6 +316,10 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_RPL_S_GT1_1, PCI_DID_INTEL_RPL_S_GT1_2, PCI_DID_INTEL_RPL_S_GT1_3, + PCI_DID_INTEL_RPL_HX_GT1, + PCI_DID_INTEL_RPL_HX_GT2, + PCI_DID_INTEL_RPL_HX_GT3, + PCI_DID_INTEL_RPL_HX_GT4, 0, }; diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 1c66649e7c..58d4dbebf4 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -436,6 +436,14 @@ static const unsigned short systemagent_ids[] = { PCI_DID_INTEL_ADL_N_ID_2, PCI_DID_INTEL_ADL_N_ID_3, PCI_DID_INTEL_ADL_N_ID_4, + PCI_DID_INTEL_RPL_HX_ID_1, + PCI_DID_INTEL_RPL_HX_ID_2, + PCI_DID_INTEL_RPL_HX_ID_3, + PCI_DID_INTEL_RPL_HX_ID_4, + PCI_DID_INTEL_RPL_HX_ID_5, + PCI_DID_INTEL_RPL_HX_ID_6, + PCI_DID_INTEL_RPL_HX_ID_7, + PCI_DID_INTEL_RPL_HX_ID_8, PCI_DID_INTEL_RPL_S_ID_1, PCI_DID_INTEL_RPL_S_ID_2, PCI_DID_INTEL_RPL_S_ID_3, |