diff options
Diffstat (limited to 'src/soc/qualcomm/sc7280/include')
| -rw-r--r-- | src/soc/qualcomm/sc7280/include/soc/addressmap.h | 27 | ||||
| -rw-r--r-- | src/soc/qualcomm/sc7280/include/soc/qcom_qup_se.h | 43 |
2 files changed, 70 insertions, 0 deletions
diff --git a/src/soc/qualcomm/sc7280/include/soc/addressmap.h b/src/soc/qualcomm/sc7280/include/soc/addressmap.h index 14c83fe7da..599d03f7b6 100644 --- a/src/soc/qualcomm/sc7280/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7280/include/soc/addressmap.h @@ -28,4 +28,31 @@ #define SDC1_TLMM_CFG_ADDR 0x0F1B3000 #define SDC2_TLMM_CFG_ADDR 0x0F1B4000 +/* + * QUP SERIAL ENGINE BASE ADDRESSES + */ +/* QUPV3_0 */ +#define QUP_SERIAL0_BASE 0x00980000 +#define QUP_SERIAL1_BASE 0x00984000 +#define QUP_SERIAL2_BASE 0x00988000 +#define QUP_SERIAL3_BASE 0x0098C000 +#define QUP_SERIAL4_BASE 0x00990000 +#define QUP_SERIAL5_BASE 0x00994000 +#define QUP_SERIAL6_BASE 0x00998000 +#define QUP_SERIAL7_BASE 0x0099C000 +#define QUP_WRAP0_BASE 0x009C0000 +#define QUP_0_GSI_BASE 0x00904000 + +/* QUPV3_1 */ +#define QUP_SERIAL8_BASE 0x00A80000 +#define QUP_SERIAL9_BASE 0x00A84000 +#define QUP_SERIAL10_BASE 0x00A88000 +#define QUP_SERIAL11_BASE 0x00A8C000 +#define QUP_SERIAL12_BASE 0x00A90000 +#define QUP_SERIAL13_BASE 0x00A94000 +#define QUP_SERIAL14_BASE 0x00A98000 +#define QUP_SERIAL15_BASE 0x00A9C000 +#define QUP_WRAP1_BASE 0x00AC0000 +#define QUP_1_GSI_BASE 0x00A04000 + #endif /* __SOC_QUALCOMM_SC7280_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7280/include/soc/qcom_qup_se.h b/src/soc/qualcomm/sc7280/include/soc/qcom_qup_se.h new file mode 100644 index 0000000000..08cc2e5c01 --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/qcom_qup_se.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_QCOM_QUP_SE_H__ +#define __SOC_QCOM_QUP_SE_H__ + +#include <console/console.h> +#include <device/mmio.h> +#include <gpio.h> +#include <soc/addressmap.h> +#include <timer.h> +#include <types.h> + +enum qup_se { + QUPV3_0_SE0, + QUPV3_0_SE1, + QUPV3_0_SE2, + QUPV3_0_SE3, + QUPV3_0_SE4, + QUPV3_0_SE5, + QUPV3_0_SE6, + QUPV3_0_SE7, + QUPV3_1_SE0, + QUPV3_1_SE1, + QUPV3_1_SE2, + QUPV3_1_SE3, + QUPV3_1_SE4, + QUPV3_1_SE5, + QUPV3_1_SE6, + QUPV3_1_SE7, + QUPV3_SE_MAX, +}; + +struct qup { + struct qup_regs *regs; + gpio_t pin[4]; + u8 func[4]; +}; + +extern struct qup qup[QUPV3_SE_MAX]; + +#define MAX_OFFSET_CFG_REG 0x000001c4 + +#endif /* __SOC_QCOM_QUP_SE_H__ */ |