summaryrefslogtreecommitdiff
path: root/src/soc/intel/xeon_sp/spr/chipset.cb
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/intel/xeon_sp/spr/chipset.cb')
-rw-r--r--src/soc/intel/xeon_sp/spr/chipset.cb16
1 files changed, 0 insertions, 16 deletions
diff --git a/src/soc/intel/xeon_sp/spr/chipset.cb b/src/soc/intel/xeon_sp/spr/chipset.cb
index 9a913d96dc..79a85965ff 100644
--- a/src/soc/intel/xeon_sp/spr/chipset.cb
+++ b/src/soc/intel/xeon_sp/spr/chipset.cb
@@ -1,22 +1,6 @@
## SPDX-License-Identifier: GPL-2.0-or-later
chip soc/intel/xeon_sp/spr
- register "pirqa_routing" = "PCH_IRQ11"
- register "pirqb_routing" = "PCH_IRQ10"
- register "pirqc_routing" = "PCH_IRQ11"
- register "pirqd_routing" = "PCH_IRQ11"
- register "pirqe_routing" = "PCH_IRQ11"
- register "pirqf_routing" = "PCH_IRQ11"
- register "pirqg_routing" = "PCH_IRQ11"
- register "pirqh_routing" = "PCH_IRQ11"
-
- # configure device interrupt routing
- register "ir00_routing" = "0x3210" # IR00, Dev31
- register "ir01_routing" = "0x3210" # IR01, Dev30
- register "ir02_routing" = "0x3210" # IR02, Dev29
- register "ir03_routing" = "0x3210" # IR03, Dev28
- register "ir04_routing" = "0x3210" # IR04, Dev27
-
# configure interrupt polarity control
register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow
register "ipc1" = "0x00000000" # IPC1