diff options
| author | Jonathan Zhang <jonzhang@meta.com> | 2023-01-25 11:35:03 -0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-04-01 09:28:05 +0000 |
| commit | d80e6f2ecaedf9bb06380c2a342a9d49b9b129f6 (patch) | |
| tree | 890af8004c48cd3da2dee2a69d5fa81c3cfc1f7a /src/soc/intel/xeon_sp/spr/chipset.cb | |
| parent | 4f9753e4808ac33ab19e126585abece718b7c6f8 (diff) | |
soc/intel/xeon_sp/spr: Add ACPI support for Sapphire Rapids
Add ACPI support for Sapphire Rapids. Passes FWTS ACPI tests.
The code was written from scratch because there are Xeon-SP specific
implementation especially Integrated Input/Output (IIO).
Change-Id: Ic2a9be0222e122ae087b9cc8e1859d257e3411d6
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71967
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/spr/chipset.cb')
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/chipset.cb | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/src/soc/intel/xeon_sp/spr/chipset.cb b/src/soc/intel/xeon_sp/spr/chipset.cb index 9a913d96dc..79a85965ff 100644 --- a/src/soc/intel/xeon_sp/spr/chipset.cb +++ b/src/soc/intel/xeon_sp/spr/chipset.cb @@ -1,22 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later chip soc/intel/xeon_sp/spr - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - - # configure device interrupt routing - register "ir00_routing" = "0x3210" # IR00, Dev31 - register "ir01_routing" = "0x3210" # IR01, Dev30 - register "ir02_routing" = "0x3210" # IR02, Dev29 - register "ir03_routing" = "0x3210" # IR03, Dev28 - register "ir04_routing" = "0x3210" # IR04, Dev27 - # configure interrupt polarity control register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow register "ipc1" = "0x00000000" # IPC1 |