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path: root/src/soc/intel/tigerlake/fsp_params_tgl.c
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Diffstat (limited to 'src/soc/intel/tigerlake/fsp_params_tgl.c')
-rw-r--r--src/soc/intel/tigerlake/fsp_params_tgl.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index 7230a4c7e0..33abac4411 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -174,8 +174,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchLanEnable = dev->enabled;
/* CNVi */
- params->CnviMode = config->CnviMode;
- params->CnviBtCore = config->CnviBtCore;
+ dev = pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI);
+ if (dev)
+ params->CnviMode = dev->enabled;
+ else
+ params->CnviMode = 0;
/* Legacy 8254 timer support */
params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;