aboutsummaryrefslogtreecommitdiff
path: root/src/soc/intel/broadwell/stage_cache.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/intel/broadwell/stage_cache.c')
-rw-r--r--src/soc/intel/broadwell/stage_cache.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/stage_cache.c b/src/soc/intel/broadwell/stage_cache.c
index 03c63575d0..dc59ab7756 100644
--- a/src/soc/intel/broadwell/stage_cache.c
+++ b/src/soc/intel/broadwell/stage_cache.c
@@ -21,7 +21,7 @@
void stage_cache_external_region(void **base, size_t *size)
{
/* The ramstage cache lives in the TSEG region.
- * The top of ram is defined to be the TSEG base address. */
+ * The top of RAM is defined to be the TSEG base address. */
u32 offset = smm_region_size();
offset -= CONFIG_IED_REGION_SIZE;
offset -= CONFIG_SMM_RESERVED_SIZE;