diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-07-29 18:31:16 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-31 19:27:53 +0200 |
| commit | 038e7247dc9705ff2d47dd90ec9a807f6feb52ba (patch) | |
| tree | 8cca6a6db31d20a8e045ee5892e8f9cb8de43f8d /src/soc/intel/broadwell/stage_cache.c | |
| parent | f9e7d1b0ca7282a0d51313a68f90e9298c0c46c6 (diff) | |
src/soc: Capitalize CPU, ACPI, RAM and ROM
Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15963
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/stage_cache.c')
| -rw-r--r-- | src/soc/intel/broadwell/stage_cache.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/stage_cache.c b/src/soc/intel/broadwell/stage_cache.c index 03c63575d0..dc59ab7756 100644 --- a/src/soc/intel/broadwell/stage_cache.c +++ b/src/soc/intel/broadwell/stage_cache.c @@ -21,7 +21,7 @@ void stage_cache_external_region(void **base, size_t *size) { /* The ramstage cache lives in the TSEG region. - * The top of ram is defined to be the TSEG base address. */ + * The top of RAM is defined to be the TSEG base address. */ u32 offset = smm_region_size(); offset -= CONFIG_IED_REGION_SIZE; offset -= CONFIG_SMM_RESERVED_SIZE; |