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Diffstat (limited to 'src/soc/intel/alderlake')
-rw-r--r--src/soc/intel/alderlake/Kconfig1
-rw-r--r--src/soc/intel/alderlake/fsp_params.c8
2 files changed, 1 insertions, 8 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 0b28938401..915dd3f381 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -24,6 +24,7 @@ config CPU_SPECIFIC_OPTIONS
select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
select FSP_M_XIP
select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
+ select FSPS_HAS_ARCH_UPD
select GENERIC_GPIO_LIB
select HAVE_FSP_GOP
select INTEL_DESCRIPTOR_MODE_CAPABLE
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 107d22e9e4..541a9612d8 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -672,12 +672,6 @@ static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg,
config->ext_fivr_settings.vnn_icc_max_ma;
}
-static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg)
-{
- /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */
- s_arch_cfg->EnableMultiPhaseSiliconInit = 1;
-}
-
static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
struct soc_intel_alderlake_config *config)
{
@@ -718,10 +712,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
struct soc_intel_alderlake_config *config;
FSP_S_CONFIG *s_cfg = &supd->FspsConfig;
- FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd;
config = config_of_soc();
- arch_silicon_init_params(s_arch_cfg);
soc_silicon_init_params(s_cfg, config);
mainboard_silicon_init_params(s_cfg);
}