6 files changed, 4 insertions, 22 deletions

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 0b28938401..915dd3f381 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -24,6 +24,7 @@ config CPU_SPECIFIC_OPTIONS
 	select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
 	select FSP_M_XIP
 	select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
+	select FSPS_HAS_ARCH_UPD
 	select GENERIC_GPIO_LIB
 	select HAVE_FSP_GOP
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 107d22e9e4..541a9612d8 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -672,12 +672,6 @@ static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg,
 			config->ext_fivr_settings.vnn_icc_max_ma;
 }
 
-static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg)
-{
-	/* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */
-	s_arch_cfg->EnableMultiPhaseSiliconInit = 1;
-}
-
 static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
 		struct soc_intel_alderlake_config *config)
 {
@@ -718,10 +712,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 {
 	struct soc_intel_alderlake_config *config;
 	FSP_S_CONFIG *s_cfg = &supd->FspsConfig;
-	FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd;
 
 	config = config_of_soc();
-	arch_silicon_init_params(s_arch_cfg);
 	soc_silicon_init_params(s_cfg, config);
 	mainboard_silicon_init_params(s_cfg);
 }
diff --git a/src/soc/intel/common/block/tcss/Kconfig b/src/soc/intel/common/block/tcss/Kconfig
index 3eb0931611..2e679138cd 100644
--- a/src/soc/intel/common/block/tcss/Kconfig
+++ b/src/soc/intel/common/block/tcss/Kconfig
@@ -1,5 +1,6 @@
 config SOC_INTEL_COMMON_BLOCK_TCSS
 	def_bool n
+	select FSPS_USE_MULTI_PHASE_INIT
 	help
 	  Sets up USB2/3 port mapping in TCSS MUX and sets MUX to disconnect state
 
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index 11b146b577..18db9359ce 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -204,12 +204,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	mainboard_silicon_init_params(params);
 }
 
-/* Disable Multiphase Si init */
-int soc_fsp_multi_phase_init_is_enable(void)
-{
-	return 0;
-}
-
 /* Mainboard GPIO Configuration */
 __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 {
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index bb100df633..892363b75c 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -565,8 +565,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 				config->PchPmSlpS3MinAssert, config->PchPmSlpAMinAssert,
 				config->PchPmPwrCycDur);
 
-	/* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */
-	params->EnableMultiPhaseSiliconInit = 1;
+	/* Override EnableMultiPhaseSiliconInit prior calling MultiPhaseSiInit */
+	params->EnableMultiPhaseSiliconInit = fsp_is_multi_phase_init_enabled();
 
 	/* Disable C1 C-state Demotion */
 	params->C1StateAutoDemotion = 0;
diff --git a/src/soc/intel/xeon_sp/cpx/ramstage.c b/src/soc/intel/xeon_sp/cpx/ramstage.c
index 1e0ba008c2..cd1b038b52 100644
--- a/src/soc/intel/xeon_sp/cpx/ramstage.c
+++ b/src/soc/intel/xeon_sp/cpx/ramstage.c
@@ -1,13 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <fsp/api.h>
 #include <smbios.h>
 
-int soc_fsp_multi_phase_init_is_enable(void)
-{
-	return 0;
-}
-
 unsigned int smbios_cpu_get_max_speed_mhz(void)
 {
 	return 3900;