diff options
Diffstat (limited to 'src/soc/intel/alderlake/include')
-rw-r--r-- | src/soc/intel/alderlake/include/soc/irq.h | 61 | ||||
-rw-r--r-- | src/soc/intel/alderlake/include/soc/pci_devs.h | 1 |
2 files changed, 1 insertions, 61 deletions
diff --git a/src/soc/intel/alderlake/include/soc/irq.h b/src/soc/intel/alderlake/include/soc/irq.h index 9d471fd90b..59727a68ca 100644 --- a/src/soc/intel/alderlake/include/soc/irq.h +++ b/src/soc/intel/alderlake/include/soc/irq.h @@ -9,65 +9,4 @@ #define PCH_IRQ10 10 #define PCH_IRQ11 11 -#define LPSS_I2C0_IRQ 27 -#define LPSS_I2C1_IRQ 40 -#define LPSS_I2C2_IRQ 29 -#define LPSS_I2C3_IRQ 30 -#define LPSS_I2C4_IRQ 31 -#define LPSS_I2C5_IRQ 32 -#define LPSS_SPI0_IRQ 36 -#define LPSS_SPI1_IRQ 37 -#define LPSS_SPI2_IRQ 39 - -#define LPSS_UART0_IRQ 16 -#define LPSS_UART1_IRQ 17 -#define LPSS_UART2_IRQ 33 -#define LPSS_UART3_IRQ 25 - -#define TRACEHUB_IRQ 16 - -#define PCIE_1_IRQ 16 -#define PCIE_2_IRQ 17 -#define PCIE_3_IRQ 18 -#define PCIE_4_IRQ 19 -#define PCIE_5_IRQ 16 -#define PCIE_6_IRQ 17 -#define PCIE_7_IRQ 18 -#define PCIE_8_IRQ 19 -#define PCIE_9_IRQ 16 -#define PCIE_10_IRQ 17 -#define PCIE_11_IRQ 18 -#define PCIE_12_IRQ 19 - -#define SATA_IRQ 16 - -#define xHCI_IRQ 16 -#define xDCI_IRQ 17 - -#define THC0_IRQ 23 -#define THC1_IRQ 22 - -#define ISH_IRQ 26 - -#define CPU_xHCI_IRQ 16 -#define CPU_xDCI_IRQ 17 - -#define TBT_PCIe0_IRQ 16 -#define TBT_PCIe1_IRQ 17 -#define TBT_PCIe2_IRQ 18 -#define TBT_PCIe3_IRQ 19 - -#define HECI_1_IRQ 16 -#define HECI_2_IRQ 17 -#define CSME_IDE_IRQ 18 -#define CSME_KT_IRQ 19 -#define HECI_3_IRQ 16 -#define HECI_4_IRQ 19 - -#define PEG_IRQ 16 -#define IGFX_IRQ 16 -#define THERMAL_IRQ 16 -#define IPU_IRQ 16 -#define GNA_IRQ 16 - #endif diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h index f2c2fcb73e..730808d1ea 100644 --- a/src/soc/intel/alderlake/include/soc/pci_devs.h +++ b/src/soc/intel/alderlake/include/soc/pci_devs.h @@ -77,6 +77,7 @@ #define SA_DEV_VMD PCI_DEV(0, SA_DEV_SLOT_VMD, 0) /* PCH Devices */ +#define MIN_PCH_SLOT PCH_DEV_SLOT_SIO0 #define PCH_DEV_SLOT_SIO0 0x10 #define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 0) #define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 1) |