diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/acpi/pci_irqs.asl | 147 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/acpi/southbridge.asl | 3 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/chip.c | 17 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 188 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/irq.h | 61 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/pci_devs.h | 1 |
7 files changed, 206 insertions, 212 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index a146a7792b..2e7049ff27 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -58,6 +58,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_MEMINIT select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT diff --git a/src/soc/intel/alderlake/acpi/pci_irqs.asl b/src/soc/intel/alderlake/acpi/pci_irqs.asl deleted file mode 100644 index 3fdd0775ed..0000000000 --- a/src/soc/intel/alderlake/acpi/pci_irqs.asl +++ /dev/null @@ -1,147 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <soc/irq.h> - -Name (PICP, Package () { - /* D31: HDA, SMBus, TraceHub, GbE */ - Package(){0x001FFFFF, 0, 0, TRACEHUB_IRQ }, - /* D30: UART0, UART1, SPI0, SPI1 */ - Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, - Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, - Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, - Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, - /* D29: RP9 ~ RP12 */ - Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ }, - Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ }, - Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ }, - Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ }, - /* D28: RP1 ~ RP8 */ - Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, /* RP 1 and 5 */ - Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, /* RP 2 and 6 */ - Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, /* RP 3 and 7 */ - Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, /* RP 4 and 8 */ - /* D25: I2C4, I2C5, UART2 */ - Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, - Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, - Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, - /* D23: SATA */ - Package(){0x0017FFFF, 0, 0, SATA_IRQ }, - /* D22: CSME */ - Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, - Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, - Package(){0x0016FFFF, 2, 0, CSME_IDE_IRQ }, - Package(){0x0016FFFF, 3, 0, CSME_KT_IRQ }, - /* D21: I2C0 ~ I2C3 */ - Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, - Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, - Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, - Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, - /* D20: xHCI, xDCI, SRAM, CNVI_WIFI */ - Package(){0x0014FFFF, 0, 0, xHCI_IRQ }, - Package(){0x0014FFFF, 1, 0, xDCI_IRQ }, - /* D18: ISH, SPI2 */ - Package(){0x0012FFFF, 0, 0, ISH_IRQ }, - Package(){0x0012FFFF, 1, 0, LPSS_SPI2_IRQ }, - /* D17: UART3 */ - Package(){0x0011FFFF, 0, 0, LPSS_UART3_IRQ }, - /* D16: THC0, THC1 */ - Package(){0x0010FFFF, 0, 0, THC0_IRQ }, - Package(){0x0010FFFF, 1, 0, THC1_IRQ }, - /* D13: xHCI, xDCI */ - Package(){0x000DFFFF, 0, 0, CPU_xHCI_IRQ }, - Package(){0x000DFFFF, 1, 0, CPU_xDCI_IRQ }, - /* D8: GNA */ - Package(){0x0008FFFF, 0, 0, GNA_IRQ }, - /* D7: TBT PCIe */ - Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ }, - Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ }, - Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ }, - Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ }, - /* D6: PEG60 */ - Package(){0x0006FFFF, 0, 0, PEG_IRQ }, - /* D5: IPU Device */ - Package(){0x0005FFFF, 0, 0, IPU_IRQ }, - /* D4: Thermal Device */ - Package(){0x0004FFFF, 0, 0, THERMAL_IRQ }, - /* D2: IGFX */ - Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, -}) - -Name (PICN, Package () { - /* D31: HDA, SMBUS, TRACEHUB */ - Package(){0x001FFFFF, 0, 0, 11 }, - Package(){0x001FFFFF, 1, 0, 10 }, - Package(){0x001FFFFF, 2, 0, 11 }, - Package(){0x001FFFFF, 3, 0, 11 }, - /* D30: UART0, UART1, SPI0, SPI1 */ - Package(){0x001EFFFF, 0, 0, 11 }, - Package(){0x001EFFFF, 1, 0, 10 }, - Package(){0x001EFFFF, 2, 0, 11 }, - Package(){0x001EFFFF, 3, 0, 11 }, - /* D29: RP9 ~ RP12 */ - Package(){0x001DFFFF, 0, 0, 11 }, - Package(){0x001DFFFF, 1, 0, 10 }, - Package(){0x001DFFFF, 2, 0, 11 }, - Package(){0x001DFFFF, 3, 0, 11 }, - /* D28: RP1 ~ RP8 */ - Package(){0x001CFFFF, 0, 0, 11 }, - Package(){0x001CFFFF, 1, 0, 10 }, - Package(){0x001CFFFF, 2, 0, 11 }, - Package(){0x001CFFFF, 3, 0, 11 }, - /* D25: I2C4, I2C5, UART2 */ - Package(){0x0019FFFF, 0, 0, 11 }, - Package(){0x0019FFFF, 1, 0, 10 }, - Package(){0x0019FFFF, 2, 0, 11 }, - /* D23: SATA */ - Package(){0x0017FFFF, 0, 0, 11 }, - /* D22: CSME */ - Package(){0x0016FFFF, 0, 0, 11 }, - Package(){0x0016FFFF, 1, 0, 10 }, - Package(){0x0016FFFF, 2, 0, 11 }, - Package(){0x0016FFFF, 3, 0, 11 }, - /* D21: I2C0 ~ I2C3 */ - Package(){0x0015FFFF, 0, 0, 11 }, - Package(){0x0015FFFF, 1, 0, 10 }, - Package(){0x0015FFFF, 2, 0, 11 }, - Package(){0x0015FFFF, 3, 0, 11 }, - /* D20: xHCI, xDCI, SRAM, CNVI_WIFI */ - Package(){0x0014FFFF, 0, 0, 11 }, - Package(){0x0014FFFF, 1, 0, 10 }, - Package(){0x0014FFFF, 2, 0, 11 }, - /* D19: SPI3 */ - Package(){0x0013FFFF, 0, 0, 11 }, - /* D18: ISH, SPI2 */ - Package(){0x0012FFFF, 0, 0, 11 }, - Package(){0x0012FFFF, 1, 0, 10 }, - /* D17: UART3 */ - Package(){0x0011FFFF, 0, 0, 11 }, - /* D16: THC0, THC1 */ - Package(){0x0010FFFF, 0, 0, 11 }, - Package(){0x0010FFFF, 1, 0, 10 }, - /* D13: xHCI, xDCI */ - Package(){0x000DFFFF, 0, 0, 11 }, - Package(){0x000DFFFF, 1, 0, 10 }, - /* D8: GNA */ - Package(){0x0008FFFF, 0, 0, 11 }, - /* D7: TBT PCIe */ - Package(){0x0007FFFF, 0, 0, 11 }, - Package(){0x0007FFFF, 1, 0, 10 }, - Package(){0x0007FFFF, 2, 0, 11 }, - Package(){0x0007FFFF, 3, 0, 11 }, - /* D6: PEG60 */ - Package(){0x0006FFFF, 0, 0, 11 }, - /* D5: IPU Device */ - Package(){0x0005FFFF, 0, 0, 11 }, - /* D4: Thermal Device */ - Package(){0x0004FFFF, 0, 0, 11 }, - /* D2: IGFX */ - Package(){0x0002FFFF, 0, 0, 11 }, -}) - -Method (_PRT) -{ - If (PICM) { - Return (^PICP) - } Else { - Return (^PICN) - } -} diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl index 3a53f2c9d1..59bcf7461f 100644 --- a/src/soc/intel/alderlake/acpi/southbridge.asl +++ b/src/soc/intel/alderlake/acpi/southbridge.asl @@ -5,9 +5,6 @@ #include <soc/itss.h> #include <soc/pcr_ids.h> -/* PCI IRQ assignment */ -#include "pci_irqs.asl" - /* PCR access */ #include <soc/intel/common/acpi/pcr.asl> diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index f4d02412eb..88b31954e6 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -7,6 +7,7 @@ #include <intelblocks/acpi.h> #include <intelblocks/cfg.h> #include <intelblocks/gpio.h> +#include <intelblocks/irq.h> #include <intelblocks/itss.h> #include <intelblocks/pcie_rp.h> #include <intelblocks/xdci.h> @@ -137,6 +138,19 @@ void soc_init_pre_device(void *chip_info) pcie_rp_update_devicetree(get_pch_pcie_rp_table()); } +static void cpu_fill_ssdt(const struct device *dev) +{ + if (!generate_pin_irq_map()) + printk(BIOS_ERR, "ERROR: Failed to generate ACPI _PRT table!\n"); + + generate_cpu_entries(dev); +} + +static void cpu_set_north_irqs(struct device *dev) +{ + irq_program_non_pch(); +} + static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, @@ -149,8 +163,9 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, + .enable_resources = cpu_set_north_irqs, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt = generate_cpu_entries, + .acpi_fill_ssdt = cpu_fill_ssdt, #endif }; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 3d38fb9f2d..612bc4ed31 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -8,6 +8,7 @@ #include <fsp/api.h> #include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> +#include <intelblocks/irq.h> #include <intelblocks/lpss.h> #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> @@ -19,6 +20,7 @@ #include <soc/pcie.h> #include <soc/ramstage.h> #include <soc/soc_chip.h> +#include <stdlib.h> #include <string.h> /* THC assignment definition */ @@ -30,6 +32,177 @@ #define DEF_DMVAL 15 #define DEF_DITOVAL 625 +static const struct slot_irq_constraints irq_constraints[] = { + { + .slot = SA_DEV_SLOT_IGD, + .fns = { + ANY_PIRQ(SA_DEVFN_IGD), + }, + }, + { + .slot = SA_DEV_SLOT_DPTF, + .fns = { + ANY_PIRQ(SA_DEVFN_DPTF), + }, + }, + { + .slot = SA_DEV_SLOT_IPU, + .fns = { + ANY_PIRQ(SA_DEVFN_IPU), + }, + }, + { + .slot = SA_DEV_SLOT_CPU_6, + .fns = { + ANY_PIRQ(SA_DEVFN_CPU_PCIE6_0), + ANY_PIRQ(SA_DEVFN_CPU_PCIE6_2), + }, + }, + { + .slot = SA_DEV_SLOT_TBT, + .fns = { + ANY_PIRQ(SA_DEVFN_TBT0), + ANY_PIRQ(SA_DEVFN_TBT1), + ANY_PIRQ(SA_DEVFN_TBT2), + ANY_PIRQ(SA_DEVFN_TBT3), + }, + }, + { + .slot = SA_DEV_SLOT_TCSS, + .fns = { + ANY_PIRQ(SA_DEVFN_TCSS_XHCI), + }, + }, + { + .slot = PCH_DEV_SLOT_ISH, + .fns = { + DIRECT_IRQ(PCH_DEVFN_ISH), + DIRECT_IRQ(PCH_DEVFN_GSPI2), + }, + }, + { + .slot = PCH_DEV_SLOT_XHCI, + .fns = { + ANY_PIRQ(PCH_DEVFN_XHCI), + ANY_PIRQ(PCH_DEVFN_CNVI_WIFI), + }, + }, + { + .slot = PCH_DEV_SLOT_SIO3, + .fns = { + DIRECT_IRQ(PCH_DEVFN_I2C0), + DIRECT_IRQ(PCH_DEVFN_I2C1), + DIRECT_IRQ(PCH_DEVFN_I2C2), + DIRECT_IRQ(PCH_DEVFN_I2C3), + }, + }, + { + .slot = PCH_DEV_SLOT_CSE, + .fns = { + ANY_PIRQ(PCH_DEVFN_CSE), + ANY_PIRQ(PCH_DEVFN_CSE_2), + ANY_PIRQ(PCH_DEVFN_CSE_IDER), + ANY_PIRQ(PCH_DEVFN_CSE_KT), + ANY_PIRQ(PCH_DEVFN_CSE_3), + ANY_PIRQ(PCH_DEVFN_CSE_4), + }, + }, + { + .slot = PCH_DEV_SLOT_SATA, + .fns = { + ANY_PIRQ(PCH_DEVFN_SATA), + }, + }, + { + .slot = PCH_DEV_SLOT_SIO4, + .fns = { + DIRECT_IRQ(PCH_DEVFN_I2C4), + DIRECT_IRQ(PCH_DEVFN_I2C5), + DIRECT_IRQ(PCH_DEVFN_UART2), + }, + }, + { + .slot = PCH_DEV_SLOT_PCIE, + .fns = { + FIXED_INT_PIRQ(PCH_DEVFN_PCIE1, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE2, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE3, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE4, PCI_INT_D, PIRQ_D), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE5, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE6, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE7, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE8, PCI_INT_D, PIRQ_D), + }, + }, + { + .slot = PCH_DEV_SLOT_PCIE_1, + .fns = { + FIXED_INT_PIRQ(PCH_DEVFN_PCIE9, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE10, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE11, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE12, PCI_INT_D, PIRQ_D), + }, + }, + { + .slot = PCH_DEV_SLOT_SIO5, + .fns = { + FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART0, PCI_INT_A), + FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART1, PCI_INT_B), + ANY_PIRQ(PCH_DEVFN_GSPI0), + ANY_PIRQ(PCH_DEVFN_GSPI1), + }, + }, + { + .slot = PCH_DEV_SLOT_ESPI, + .fns = { + ANY_PIRQ(PCH_DEVFN_HDA), + ANY_PIRQ(PCH_DEVFN_SMBUS), + ANY_PIRQ(PCH_DEVFN_GBE), + FIXED_INT_ANY_PIRQ(PCH_DEVFN_TRACEHUB, PCI_INT_A), + }, + }, +}; + +static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count) +{ + const struct pci_irq_entry *entry = get_cached_pci_irqs(); + SI_PCH_DEVICE_INTERRUPT_CONFIG *config; + size_t pch_total = 0; + size_t cfg_count = 0; + + if (!entry) + return NULL; + + /* Count PCH devices */ + while (entry) { + if (PCI_SLOT(entry->devfn) >= MIN_PCH_SLOT) + ++pch_total; + entry = entry->next; + } + + /* Convert PCH device entries to FSP format */ + config = calloc(pch_total, sizeof(*config)); + entry = get_cached_pci_irqs(); + while (entry) { + if (PCI_SLOT(entry->devfn) < MIN_PCH_SLOT) { + entry = entry->next; + continue; + } + + config[cfg_count].Device = PCI_SLOT(entry->devfn); + config[cfg_count].Function = PCI_FUNC(entry->devfn); + config[cfg_count].IntX = (SI_PCH_INT_PIN)entry->pin; + config[cfg_count].Irq = entry->irq; + ++cfg_count; + + entry = entry->next; + } + + *out_count = cfg_count; + + return config; +} + /* * Chip config parameter PcieRpL1Substates uses (UPD value + 1) * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. @@ -334,6 +507,20 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, s_cfg->PsOnEnable = 1; } +static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_alderlake_config *config) +{ + if (!assign_pci_irqs(irq_constraints, ARRAY_SIZE(irq_constraints))) + die("ERROR: Unable to assign PCI IRQs, and no _PRT table available\n"); + + size_t pch_count = 0; + const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count); + + s_cfg->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs); + s_cfg->NumOfDevIntConfig = pch_count; + printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n"); +} + static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg) { /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ @@ -367,6 +554,7 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, fill_fsps_storage_params, fill_fsps_pcie_params, fill_fsps_misc_power_params, + fill_fsps_irq_params, }; for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++) diff --git a/src/soc/intel/alderlake/include/soc/irq.h b/src/soc/intel/alderlake/include/soc/irq.h index 9d471fd90b..59727a68ca 100644 --- a/src/soc/intel/alderlake/include/soc/irq.h +++ b/src/soc/intel/alderlake/include/soc/irq.h @@ -9,65 +9,4 @@ #define PCH_IRQ10 10 #define PCH_IRQ11 11 -#define LPSS_I2C0_IRQ 27 -#define LPSS_I2C1_IRQ 40 -#define LPSS_I2C2_IRQ 29 -#define LPSS_I2C3_IRQ 30 -#define LPSS_I2C4_IRQ 31 -#define LPSS_I2C5_IRQ 32 -#define LPSS_SPI0_IRQ 36 -#define LPSS_SPI1_IRQ 37 -#define LPSS_SPI2_IRQ 39 - -#define LPSS_UART0_IRQ 16 -#define LPSS_UART1_IRQ 17 -#define LPSS_UART2_IRQ 33 -#define LPSS_UART3_IRQ 25 - -#define TRACEHUB_IRQ 16 - -#define PCIE_1_IRQ 16 -#define PCIE_2_IRQ 17 -#define PCIE_3_IRQ 18 -#define PCIE_4_IRQ 19 -#define PCIE_5_IRQ 16 -#define PCIE_6_IRQ 17 -#define PCIE_7_IRQ 18 -#define PCIE_8_IRQ 19 -#define PCIE_9_IRQ 16 -#define PCIE_10_IRQ 17 -#define PCIE_11_IRQ 18 -#define PCIE_12_IRQ 19 - -#define SATA_IRQ 16 - -#define xHCI_IRQ 16 -#define xDCI_IRQ 17 - -#define THC0_IRQ 23 -#define THC1_IRQ 22 - -#define ISH_IRQ 26 - -#define CPU_xHCI_IRQ 16 -#define CPU_xDCI_IRQ 17 - -#define TBT_PCIe0_IRQ 16 -#define TBT_PCIe1_IRQ 17 -#define TBT_PCIe2_IRQ 18 -#define TBT_PCIe3_IRQ 19 - -#define HECI_1_IRQ 16 -#define HECI_2_IRQ 17 -#define CSME_IDE_IRQ 18 -#define CSME_KT_IRQ 19 -#define HECI_3_IRQ 16 -#define HECI_4_IRQ 19 - -#define PEG_IRQ 16 -#define IGFX_IRQ 16 -#define THERMAL_IRQ 16 -#define IPU_IRQ 16 -#define GNA_IRQ 16 - #endif diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h index f2c2fcb73e..730808d1ea 100644 --- a/src/soc/intel/alderlake/include/soc/pci_devs.h +++ b/src/soc/intel/alderlake/include/soc/pci_devs.h @@ -77,6 +77,7 @@ #define SA_DEV_VMD PCI_DEV(0, SA_DEV_SLOT_VMD, 0) /* PCH Devices */ +#define MIN_PCH_SLOT PCH_DEV_SLOT_SIO0 #define PCH_DEV_SLOT_SIO0 0x10 #define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 0) #define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 1) |