diff options
Diffstat (limited to 'src/soc/amd/common/block/lpc')
| -rw-r--r-- | src/soc/amd/common/block/lpc/espi_util.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 0878fb7663..152cdd9001 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -98,6 +98,27 @@ static int espi_get_unused_io_window(void) return -1; } +void espi_clear_decodes(void) +{ + unsigned int idx; + + /* First turn off all enable bits, then zero base, range, and size registers */ + /* + * There is currently a bug where the SMU will lock up at times if the port80h enable + * bit is cleared. See b/183974365 + */ + espi_write16(ESPI_DECODE, (espi_read16(ESPI_DECODE) & ESPI_DECODE_IO_0x80_EN)); + + for (idx = 0; idx < ESPI_GENERIC_IO_WIN_COUNT; idx++) { + espi_write16(ESPI_IO_RANGE_BASE(idx), 0); + espi_write8(ESPI_IO_RANGE_SIZE(idx), 0); + } + for (idx = 0; idx < ESPI_GENERIC_MMIO_WIN_COUNT; idx++) { + espi_write32(ESPI_MMIO_RANGE_BASE(idx), 0); + espi_write16(ESPI_MMIO_RANGE_SIZE(idx), 0); + } +} + /* * Returns decode enable bits for standard IO port addresses. If port address is not supported * by standard decode or if the size of window is not 1, then it returns -1. |