soc/amd/common: Add func to clear eSPI IO & memory decode ranges

Previously, the eSPI code would only add to existing decode ranges, and
there wasn't any way to clear ranges.  This clears all the ranges so
the eSPI configuration can start fresh.

BUG=b:183207262, b:183974365
TEST=Verify on Guybrush

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ic4e67c40d34915505bdd5b431a064d2c7b6bbc70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

1 files changed, 21 insertions, 0 deletions

diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c
index 0878fb7663..152cdd9001 100644
--- a/src/soc/amd/common/block/lpc/espi_util.c
+++ b/src/soc/amd/common/block/lpc/espi_util.c
@@ -98,6 +98,27 @@ static int espi_get_unused_io_window(void)
 	return -1;
 }
 
+void espi_clear_decodes(void)
+{
+	unsigned int idx;
+
+	/* First turn off all enable bits, then zero base, range, and size registers */
+	/*
+	 * There is currently a bug where the SMU will lock up at times if the port80h enable
+	 * bit is cleared.  See b/183974365
+	 */
+	espi_write16(ESPI_DECODE, (espi_read16(ESPI_DECODE) & ESPI_DECODE_IO_0x80_EN));
+
+	for (idx = 0; idx < ESPI_GENERIC_IO_WIN_COUNT; idx++) {
+		espi_write16(ESPI_IO_RANGE_BASE(idx), 0);
+		espi_write8(ESPI_IO_RANGE_SIZE(idx), 0);
+	}
+	for (idx = 0; idx < ESPI_GENERIC_MMIO_WIN_COUNT; idx++) {
+		espi_write32(ESPI_MMIO_RANGE_BASE(idx), 0);
+		espi_write16(ESPI_MMIO_RANGE_SIZE(idx), 0);
+	}
+}
+
 /*
  * Returns decode enable bits for standard IO port addresses. If port address is not supported
  * by standard decode or if the size of window is not 1, then it returns -1.