diff options
Diffstat (limited to 'src/northbridge/via')
| -rw-r--r-- | src/northbridge/via/cn400/raminit.c | 4 | ||||
| -rw-r--r-- | src/northbridge/via/vt8623/raminit.c | 24 | ||||
| -rw-r--r-- | src/northbridge/via/vx800/uma_ram_setting.c | 4 | ||||
| -rw-r--r-- | src/northbridge/via/vx900/chrome9hd.c | 2 |
4 files changed, 17 insertions, 17 deletions
diff --git a/src/northbridge/via/cn400/raminit.c b/src/northbridge/via/cn400/raminit.c index 23a6209458..d15a6338e0 100644 --- a/src/northbridge/via/cn400/raminit.c +++ b/src/northbridge/via/cn400/raminit.c @@ -333,7 +333,7 @@ static void ddr_ram_setup(void) } } if( b & 0x04 ){ // DDR mandatory CAS 2 - if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max Mhz at CAS 2 + if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max MHz at CAS 2 //print_debug("\nWe can do CAS 2"); c = 0x10; } @@ -342,7 +342,7 @@ static void ddr_ram_setup(void) //print_debug("\nStarting at CAS 2.5"); c = 0x20; // assume CAS 2.5 if( b & 0x04){ // Should always happen - if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max Mhz at CAS 2 + if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max MHz at CAS 2 //print_debug("\nWe can do CAS 2"); c = 0x10; } diff --git a/src/northbridge/via/vt8623/raminit.c b/src/northbridge/via/vt8623/raminit.c index b5c78a1337..f281ce096c 100644 --- a/src/northbridge/via/vt8623/raminit.c +++ b/src/northbridge/via/vt8623/raminit.c @@ -21,12 +21,12 @@ /* Automatically detect and set up ddr dram on the CLE266 chipset. Assumes DDR memory, though chipset also supports SDRAM - Assumes at least 266Mhz memory as no attempt is made to clock + Assumes at least 266MHz memory as no attempt is made to clock the chipset down if slower memory is installed. So far tested on: - 256 Mb 266Mhz 1 Bank (i.e. single sided) - 256 Mb 266Mhz 2 Bank (i.e. double sided) - 512 Mb 266Mhz 2 Bank (i.e. double sided) + 256 Mb 266MHz 1 Bank (i.e. single sided) + 256 Mb 266MHz 2 Bank (i.e. double sided) + 512 Mb 266MHz 2 Bank (i.e. double sided) */ /* ported and enhanced from assembler level code in coreboot v1 */ @@ -199,13 +199,13 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) c = 0x30; /* see if we can better it */ if( b & 0x08 ){ // DDR mandatory CAS 2.5 - if( smbus_read_byte(DIMM0,23) <= 0x75 ){ // we can manage 133Mhz at CAS 2.5 + if( smbus_read_byte(DIMM0,23) <= 0x75 ){ // we can manage 133MHz at CAS 2.5 print_debug("\nWe can do CAS 2.5"); c = 0x20; } } if( b & 0x04 ){ // DDR mandatory CAS 2 - if( smbus_read_byte(DIMM0,25) <= 0x75 ){ // we can manage 133Mhz at CAS 2 + if( smbus_read_byte(DIMM0,25) <= 0x75 ){ // we can manage 133MHz at CAS 2 print_debug("\nWe can do CAS 2"); c = 0x10; } @@ -214,7 +214,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) print_debug("\nStarting at CAS 2.5"); c = 0x20; // assume CAS 2.5 if( b & 0x04){ // Should always happen - if( smbus_read_byte(DIMM0,23) <= 0x75){ // we can manage 133Mhz at CAS 2 + if( smbus_read_byte(DIMM0,23) <= 0x75){ // we can manage 133MHz at CAS 2 print_debug("\nWe can do CAS 2"); c = 0x10; } @@ -308,7 +308,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) /* CPU Frequency Device 0 Offset 54 - CPU Frequency 54[7,6] bootstraps at 0xc0 (133Mhz) + CPU Frequency 54[7,6] bootstraps at 0xc0 (133MHz) DRAM burst length = 8 54[5] */ pci_write_config8(north,0x54,0xe0); @@ -567,10 +567,10 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) Rx69 (DRAM freq) Rx58 (chip tech) Rx6a - 133Mhz 64/128Mb 0x86 - 133Mhz 256/512Mb 0x43 - 100Mhz 64/128Mb 0x65 - 100Mhz 256/512Mb 0x32 + 133MHz 64/128Mb 0x86 + 133MHz 256/512Mb 0x43 + 100MHz 64/128Mb 0x65 + 100MHz 256/512Mb 0x32 */ b = pci_read_config8(north,0x58); diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c index d404cde122..487dab466e 100644 --- a/src/northbridge/via/vx800/uma_ram_setting.c +++ b/src/northbridge/via/vx800/uma_ram_setting.c @@ -265,14 +265,14 @@ void SetUMARam(void) outb(0x68, 0x03c4); outb(VgaPortVal, 0x03c5); - // ECLK Selection (00:166Mhz, 01:185Mhz, 10:250Mhz, 11:275Mhz) + // ECLK Selection (00:166MHz, 01:185MHz, 10:250MHz, 11:275MHz) // set 3C5.5A[0]=1, address maps to secondary resgiters outb(0x5a, 0x03c4); ByteVal = inb(0x03c5); ByteVal |= 0x01; outb(ByteVal, 0x03c5); - // Set 3D5.4C[7:6] (00:166Mhz, 01:185Mhz, 10:250Mhz, 11:275Mhz) + // Set 3D5.4C[7:6] (00:166MHz, 01:185MHz, 10:250MHz, 11:275MHz) outb(0x4c, 0x03d4); ByteVal = inb(0x03d5); ByteVal = (ByteVal & 0x3F) | 0x80; diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c index bf0b278a76..fc9a202e9b 100644 --- a/src/northbridge/via/vx900/chrome9hd.c +++ b/src/northbridge/via/vx900/chrome9hd.c @@ -334,7 +334,7 @@ static void chrome9hd_enable(device_t dev) { device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); - /* FIXME: here? -=- ACLK 250Mhz */ + /* FIXME: here? -=- ACLK 250MHz */ pci_mod_config8(mcu, 0xbb, 0, 0x01); } |