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Diffstat (limited to 'src/northbridge/via/cn400/raminit.c')
-rw-r--r--src/northbridge/via/cn400/raminit.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/via/cn400/raminit.c b/src/northbridge/via/cn400/raminit.c
index 23a6209458..d15a6338e0 100644
--- a/src/northbridge/via/cn400/raminit.c
+++ b/src/northbridge/via/cn400/raminit.c
@@ -333,7 +333,7 @@ static void ddr_ram_setup(void)
}
}
if( b & 0x04 ){ // DDR mandatory CAS 2
- if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max Mhz at CAS 2
+ if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max MHz at CAS 2
//print_debug("\nWe can do CAS 2");
c = 0x10;
}
@@ -342,7 +342,7 @@ static void ddr_ram_setup(void)
//print_debug("\nStarting at CAS 2.5");
c = 0x20; // assume CAS 2.5
if( b & 0x04){ // Should always happen
- if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max Mhz at CAS 2
+ if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max MHz at CAS 2
//print_debug("\nWe can do CAS 2");
c = 0x10;
}