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Diffstat (limited to 'src/northbridge/intel/pineview/memmap.c')
-rw-r--r--src/northbridge/intel/pineview/memmap.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index c02cf35712..55d704678c 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -73,9 +73,9 @@ static uintptr_t northbridge_get_tseg_base(void)
* Depending of UMA and TSEG configuration, TSEG might start at any 1 MiB alignment.
* As this may cause very greedy MTRR setup, push CBMEM top downwards to 4 MiB boundary.
*/
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
{
- return (void *) ALIGN_DOWN(northbridge_get_tseg_base(), 4 * MiB);
+ return ALIGN_DOWN(northbridge_get_tseg_base(), 4 * MiB);
}