diff options
40 files changed, 86 insertions, 90 deletions
diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 5c3d90494f..132cb3e485 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -93,8 +93,8 @@ static void ap_romstage_main(void) halt(); } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Top of CBMEM is at highest usable DRAM address below 4GiB. */ - return (void *)restore_top_of_low_cacheable(); + return restore_top_of_low_cacheable(); } diff --git a/src/drivers/intel/fsp2_0/cbmem.c b/src/drivers/intel/fsp2_0/cbmem.c index 0efb462b40..176d256e17 100644 --- a/src/drivers/intel/fsp2_0/cbmem.c +++ b/src/drivers/intel/fsp2_0/cbmem.c @@ -3,10 +3,10 @@ #include <cbmem.h> #include <fsp/util.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { struct range_entry tolum; fsp_find_bootloader_tolum(&tolum); - return (void *)(uintptr_t)range_entry_end(&tolum); + return range_entry_end(&tolum); } diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 40a0acb510..5e2128e5f9 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -65,7 +65,7 @@ void *cbmem_top(void); * in the _cbmem_top_ptr symbol. Without CONFIG_RAMSTAGE_CBMEM_TOP_ARG the same * implementation as used in romstage will be used. */ -void *cbmem_top_chipset(void); +uintptr_t cbmem_top_chipset(void); /* Add a cbmem entry of a given size and id. These return NULL on failure. The * add function performs a find first and do not check against the original diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index a855cf18b3..91c86211f5 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -18,11 +18,11 @@ static struct imd imd; void *cbmem_top(void) { if (ENV_CREATES_CBMEM) { - static void *top; + static uintptr_t top; if (top) - return top; + return (void *)top; top = cbmem_top_chipset(); - return top; + return (void *)top; } if (ENV_POSTCAR || ENV_RAMSTAGE) return (void *)_cbmem_top_ptr; diff --git a/src/mainboard/emulation/qemu-aarch64/cbmem.c b/src/mainboard/emulation/qemu-aarch64/cbmem.c index 6b6ac720cf..389ff4ead0 100644 --- a/src/mainboard/emulation/qemu-aarch64/cbmem.c +++ b/src/mainboard/emulation/qemu-aarch64/cbmem.c @@ -4,7 +4,7 @@ #include <ramdetect.h> #include <symbols.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/src/mainboard/emulation/qemu-armv7/cbmem.c b/src/mainboard/emulation/qemu-armv7/cbmem.c index 157e443910..5c423a05bb 100644 --- a/src/mainboard/emulation/qemu-armv7/cbmem.c +++ b/src/mainboard/emulation/qemu-armv7/cbmem.c @@ -4,7 +4,7 @@ #include <symbols.h> #include <ramdetect.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/src/mainboard/emulation/qemu-i440fx/memmap.c b/src/mainboard/emulation/qemu-i440fx/memmap.c index 75ab352b69..efe83c3449 100644 --- a/src/mainboard/emulation/qemu-i440fx/memmap.c +++ b/src/mainboard/emulation/qemu-i440fx/memmap.c @@ -41,7 +41,7 @@ unsigned long qemu_get_memory_size(void) return tomk; } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { uintptr_t top = 0; @@ -56,7 +56,7 @@ void *cbmem_top_chipset(void) smm_region(&top, &smm_size); } - return (void *)top; + return top; } /* Nothing to do, MTRRs are no-op on QEMU. */ diff --git a/src/mainboard/emulation/qemu-power8/cbmem.c b/src/mainboard/emulation/qemu-power8/cbmem.c index 15c20f8de4..1c0c62b3a6 100644 --- a/src/mainboard/emulation/qemu-power8/cbmem.c +++ b/src/mainboard/emulation/qemu-power8/cbmem.c @@ -2,10 +2,9 @@ #include <cbmem.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ /* For now, last 1M of 4G */ - void *ptr = (void *) ((1ULL << 32) - 1048576); - return ptr; + return (1ULL << 32) - 1048576; } diff --git a/src/mainboard/emulation/qemu-power9/cbmem.c b/src/mainboard/emulation/qemu-power9/cbmem.c index 1b7b690883..82ae74ea3b 100644 --- a/src/mainboard/emulation/qemu-power9/cbmem.c +++ b/src/mainboard/emulation/qemu-power9/cbmem.c @@ -3,7 +3,7 @@ #include <cbmem.h> #include <ramdetect.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)(probe_ramsize(0, CONFIG_DRAM_SIZE_MB) * MiB); + return probe_ramsize(0, CONFIG_DRAM_SIZE_MB) * MiB; } diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index b1ac3d1124..0d90175a5a 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -3,14 +3,16 @@ // Use simple device model for this file even in ramstage #define __SIMPLE_DEVICE__ -#include <device/pci_ops.h> #include <arch/romstage.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> +#include <device/pci_ops.h> #include <program_loading.h> +#include <stdint.h> + #include "e7505.h" -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { const pci_devfn_t mch = PCI_DEV(0, 0, 0); uintptr_t tolm; @@ -19,7 +21,7 @@ void *cbmem_top_chipset(void) tolm = pci_read_config16(mch, TOLM) >> 11; tolm <<= 27; - return (void *)tolm; + return tolm; } void northbridge_write_smram(u8 smram); diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 28edb381a1..35ec41da46 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -104,10 +104,9 @@ static size_t northbridge_get_tseg_size(void) * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index c19cfecc73..6b75caa861 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -54,9 +54,9 @@ static uintptr_t top_of_low_usable_memory(void) return tolum; } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)top_of_low_usable_memory(); + return top_of_low_usable_memory(); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c index b6d95268ad..5cee1b4d38 100644 --- a/src/northbridge/intel/i440bx/memmap.c +++ b/src/northbridge/intel/i440bx/memmap.c @@ -8,7 +8,7 @@ #include <program_loading.h> #include "i440bx.h" -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Base of TSEG is top of usable DRAM */ /* @@ -39,7 +39,7 @@ void *cbmem_top_chipset(void) * * Source: 440BX datasheet, pages 3-28 thru 3-29. */ - unsigned long tom = pci_read_config8(NB, DRB7) * 8 * MiB; + uintptr_t tom = pci_read_config8(NB, DRB7) * 8 * MiB; int gsmrame = pci_read_config8(NB, SMRAM) & 0x8; /* T_SZ and TSEG_EN */ @@ -48,7 +48,7 @@ void *cbmem_top_chipset(void) int tseg_size = 128 * KiB * (1 << (tseg >> 1)); tom -= tseg_size; } - return (void *)tom; + return tom; } void fill_postcar_frame(struct postcar_frame *pcf) diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 1fa0358dbd..e0352fba8f 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -57,10 +57,9 @@ static size_t northbridge_get_tseg_size(void) * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); } /* Decodes used Graphics Mode Select (GMS) to kilobytes. */ diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c index 78fbae85fe..bdb76c12bb 100644 --- a/src/northbridge/intel/ironlake/memmap.c +++ b/src/northbridge/intel/ironlake/memmap.c @@ -22,9 +22,9 @@ static size_t northbridge_get_tseg_size(void) return CONFIG_SMM_TSEG_SIZE; } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)northbridge_get_tseg_base(); + return northbridge_get_tseg_base(); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index c02cf35712..55d704678c 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -73,9 +73,9 @@ static uintptr_t northbridge_get_tseg_base(void) * Depending of UMA and TSEG configuration, TSEG might start at any 1 MiB alignment. * As this may cause very greedy MTRR setup, push CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *) ALIGN_DOWN(northbridge_get_tseg_base(), 4 * MiB); + return ALIGN_DOWN(northbridge_get_tseg_base(), 4 * MiB); } diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index f667544c68..ac95ab5683 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -54,9 +54,9 @@ static uintptr_t top_of_low_usable_memory(void) return tolum; } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)top_of_low_usable_memory(); + return top_of_low_usable_memory(); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index dced902919..0b085cf6da 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -71,10 +71,9 @@ static uintptr_t northbridge_get_tseg_base(void) * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index f01574097a..7a225e1b1f 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -12,7 +12,7 @@ #include <soc/iomap.h> #include <amdblocks/biosram.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { msr_t tom = rdmsr(TOP_MEM); @@ -20,8 +20,7 @@ void *cbmem_top_chipset(void) return 0; /* 8MB alignment to keep MTRR usage low */ - return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() - - CONFIG_SMM_TSEG_SIZE, 8 * MiB); + return ALIGN_DOWN(restore_top_of_low_cacheable() - CONFIG_SMM_TSEG_SIZE, 8 * MiB); } static uintptr_t smm_region_start(void) diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c index d50fe16519..0b0c7176a8 100644 --- a/src/soc/cavium/cn81xx/cbmem.c +++ b/src/soc/cavium/cn81xx/cbmem.c @@ -5,8 +5,8 @@ #include <soc/sdram.h> #include <symbols.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Make sure not to overlap with reserved ATF scratchpad */ - return (void *)((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB); + return (uintptr_t)_dram + (sdram_size_mb() - 1) * MiB; } diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index aa8e890a04..43b96c1c34 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -16,9 +16,9 @@ static size_t smm_region_size(void) return CONFIG_SMM_TSEG_SIZE; } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *) smm_region_start(); + return smm_region_start(); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index 4a791ef181..3c3ad74b71 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -19,7 +19,7 @@ void smm_region(uintptr_t *start, size_t *size) *size = smm_region_size(); } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { uintptr_t smm_base; size_t smm_size; @@ -53,5 +53,5 @@ void *cbmem_top_chipset(void) */ smm_region(&smm_base, &smm_size); - return (void *)smm_base; + return smm_base; } diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index b467dc0a38..98c80165b0 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -29,9 +29,9 @@ static uintptr_t dpr_region_start(void) return tom; } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *) dpr_region_start(); + return dpr_region_start(); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/soc/mediatek/common/cbmem.c b/src/soc/mediatek/common/cbmem.c index f9d11e91c5..0ca9e6b802 100644 --- a/src/soc/mediatek/common/cbmem.c +++ b/src/soc/mediatek/common/cbmem.c @@ -7,7 +7,7 @@ #define MAX_DRAM_ADDRESS ((uintptr_t)4 * GiB) -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)MIN((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); + return MIN((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); } diff --git a/src/soc/nvidia/tegra124/cbmem.c b/src/soc/nvidia/tegra124/cbmem.c index 3f59f061c1..287ef62992 100644 --- a/src/soc/nvidia/tegra124/cbmem.c +++ b/src/soc/nvidia/tegra124/cbmem.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cbmem.h> +#include <commonlib/bsd/helpers.h> #include <soc/display.h> #include <soc/sdram.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL); + return (sdram_max_addressable_mb() - FB_SIZE_MB) * MiB; } diff --git a/src/soc/nvidia/tegra210/cbmem.c b/src/soc/nvidia/tegra210/cbmem.c index d9b22263ec..a56f150b26 100644 --- a/src/soc/nvidia/tegra210/cbmem.c +++ b/src/soc/nvidia/tegra210/cbmem.c @@ -3,7 +3,7 @@ #include <cbmem.h> #include <soc/addressmap.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { static uintptr_t addr; @@ -19,5 +19,5 @@ void *cbmem_top_chipset(void) addr = end_mib << 20; } - return (void *)addr; + return addr; } diff --git a/src/soc/nvidia/tegra210/ramstage.c b/src/soc/nvidia/tegra210/ramstage.c index 50249b7051..45b221b3fc 100644 --- a/src/soc/nvidia/tegra210/ramstage.c +++ b/src/soc/nvidia/tegra210/ramstage.c @@ -59,7 +59,7 @@ void ramstage_entry(void) /* Ramstage is run on a different core, so passing cbmem_top via calling arguments is not an option, but it is not a problem to call cbmem_top_chipset() again here to populate _cbmem_top_ptr. */ - _cbmem_top_ptr = (uintptr_t)cbmem_top_chipset(); + _cbmem_top_ptr = cbmem_top_chipset(); /* Jump to boot state machine in common code. */ main(); diff --git a/src/soc/qualcomm/ipq40xx/cbmem.c b/src/soc/qualcomm/ipq40xx/cbmem.c index 0ee9f9a587..c5d1a8144e 100644 --- a/src/soc/qualcomm/ipq40xx/cbmem.c +++ b/src/soc/qualcomm/ipq40xx/cbmem.c @@ -10,7 +10,7 @@ void ipq_cbmem_backing_store_ready(void) cbmem_backing_store_ready = 1; } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* * In romstage, make sure that cbmem backing store is ready before @@ -19,7 +19,7 @@ void *cbmem_top_chipset(void) * for loading ipq blobs before DRAM is initialized). */ if (cbmem_backing_store_ready == 0) - return NULL; + return 0; - return _memlayout_cbmem_top; + return (uintptr_t)_memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index a695cf827e..8196416168 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -10,7 +10,7 @@ void ipq_cbmem_backing_store_ready(void) cbmem_backing_store_ready = 1; } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* * In romstage, make sure that cbmem backing store is ready before @@ -20,7 +20,7 @@ void *cbmem_top_chipset(void) * initialized). */ if (cbmem_backing_store_ready == 0) - return NULL; + return 0; - return _memlayout_cbmem_top; + return (uintptr_t)_memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/qcs405/cbmem.c b/src/soc/qualcomm/qcs405/cbmem.c index 97ba38b630..e8bab77501 100644 --- a/src/soc/qualcomm/qcs405/cbmem.c +++ b/src/soc/qualcomm/qcs405/cbmem.c @@ -2,7 +2,7 @@ #include <cbmem.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)((uintptr_t)3 * GiB); + return (uintptr_t)3 * GiB; } diff --git a/src/soc/qualcomm/sc7180/cbmem.c b/src/soc/qualcomm/sc7180/cbmem.c index 4b9eb37861..5fff371d58 100644 --- a/src/soc/qualcomm/sc7180/cbmem.c +++ b/src/soc/qualcomm/sc7180/cbmem.c @@ -2,7 +2,7 @@ #include <cbmem.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)((uintptr_t)4 * GiB); + return (uintptr_t)4 * GiB; } diff --git a/src/soc/qualcomm/sc7280/cbmem.c b/src/soc/qualcomm/sc7280/cbmem.c index 4b9eb37861..5fff371d58 100644 --- a/src/soc/qualcomm/sc7280/cbmem.c +++ b/src/soc/qualcomm/sc7280/cbmem.c @@ -2,7 +2,7 @@ #include <cbmem.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)((uintptr_t)4 * GiB); + return (uintptr_t)4 * GiB; } diff --git a/src/soc/rockchip/common/cbmem.c b/src/soc/rockchip/common/cbmem.c index 5650114e76..172491eb57 100644 --- a/src/soc/rockchip/common/cbmem.c +++ b/src/soc/rockchip/common/cbmem.c @@ -6,8 +6,7 @@ #include <soc/sdram.h> #include <symbols.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)MIN((uintptr_t)_dram + sdram_size_mb() * MiB, - MAX_DRAM_ADDRESS); + return MIN((uintptr_t)_dram + sdram_size_mb() * MiB, MAX_DRAM_ADDRESS); } diff --git a/src/soc/samsung/exynos5250/cbmem.c b/src/soc/samsung/exynos5250/cbmem.c index 167bd80a3a..d74b414f78 100644 --- a/src/soc/samsung/exynos5250/cbmem.c +++ b/src/soc/samsung/exynos5250/cbmem.c @@ -3,7 +3,7 @@ #include <cbmem.h> #include <soc/cpu.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)(get_fb_base_kb() * KiB); + return get_fb_base_kb() * KiB; } diff --git a/src/soc/samsung/exynos5420/cbmem.c b/src/soc/samsung/exynos5420/cbmem.c index 167bd80a3a..d74b414f78 100644 --- a/src/soc/samsung/exynos5420/cbmem.c +++ b/src/soc/samsung/exynos5420/cbmem.c @@ -3,7 +3,7 @@ #include <cbmem.h> #include <soc/cpu.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)(get_fb_base_kb() * KiB); + return get_fb_base_kb() * KiB; } diff --git a/src/soc/sifive/fu540/cbmem.c b/src/soc/sifive/fu540/cbmem.c index af0413038d..53e5fcf13b 100644 --- a/src/soc/sifive/fu540/cbmem.c +++ b/src/soc/sifive/fu540/cbmem.c @@ -6,8 +6,7 @@ #include <soc/sdram.h> #include <symbols.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)MIN((uintptr_t)_dram + sdram_size_mb() * MiB, - FU540_MAXDRAM); + return MIN((uintptr_t)_dram + sdram_size_mb() * MiB, FU540_MAXDRAM); } diff --git a/src/soc/ti/am335x/cbmem.c b/src/soc/ti/am335x/cbmem.c index 170695eff8..14c927e960 100644 --- a/src/soc/ti/am335x/cbmem.c +++ b/src/soc/ti/am335x/cbmem.c @@ -4,7 +4,7 @@ #include <commonlib/bsd/helpers.h> #include <symbols.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return _dram + CONFIG_DRAM_SIZE_MB * MiB; + return (uintptr_t)_dram + CONFIG_DRAM_SIZE_MB * MiB; } diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c index 157e443910..5c423a05bb 100644 --- a/src/soc/ucb/riscv/cbmem.c +++ b/src/soc/ucb/riscv/cbmem.c @@ -4,7 +4,7 @@ #include <symbols.h> #include <ramdetect.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/tests/lib/coreboot_table-test.c b/tests/lib/coreboot_table-test.c index 16ab97f37b..aa10f6534b 100644 --- a/tests/lib/coreboot_table-test.c +++ b/tests/lib/coreboot_table-test.c @@ -243,9 +243,9 @@ void cbmem_run_init_hooks(int is_recovery) } extern uintptr_t _cbmem_top_ptr; -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)_cbmem_top_ptr; + return _cbmem_top_ptr; } #define CBMEM_SIZE (64 * KiB) diff --git a/tests/lib/imd_cbmem-test.c b/tests/lib/imd_cbmem-test.c index fe25285b68..e345c84533 100644 --- a/tests/lib/imd_cbmem-test.c +++ b/tests/lib/imd_cbmem-test.c @@ -36,9 +36,9 @@ void cbmem_run_init_hooks(int is_recovery) function_called(); } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)_cbmem_top_ptr; + return _cbmem_top_ptr; } static void *get_cbmem_ptr(void) |