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-rw-r--r--src/northbridge/intel/i945/bootblock.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c
index 9d06120ecb..60051babd3 100644
--- a/src/northbridge/intel/i945/bootblock.c
+++ b/src/northbridge/intel/i945/bootblock.c
@@ -10,10 +10,10 @@ void bootblock_early_northbridge_init(void)
/*
* The "io" variant of the config access is explicitly used to setup the PCIEXBAR
- * because CONFIG_MMCONF_SUPPORT is set to true. That way all subsequent non-explicit
+ * because CONFIG(MMCONF_SUPPORT) is set to true. That way all subsequent non-explicit
* config accesses use MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final assumption is that
- * no assembly code is using the CONFIG_MMCONF_SUPPORT option to do PCI config accesses.
+ * no assembly code is using the CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/