diff options
22 files changed, 32 insertions, 32 deletions
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index 3404e7fb4a..b56d106922 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -63,7 +63,7 @@ static void per_cpu_smm_trigger(void) } else { if (!CONFIG(SET_IA32_FC_LOCK_BIT)) printk(BIOS_INFO, - "Overriding CONFIG_SET_IA32_FC_LOCK_BIT to enable SMRR\n"); + "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n"); ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0); wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl); } diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index c6d6442da8..0eba0e384c 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -653,7 +653,7 @@ static void print_us(const char *msg, u32 val) /** * \brief Print the info in DIMM * -* Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is +* Print info about the DIMM. Useful to use when CONFIG(DEBUG_RAM_SETUP) is * selected, or for a purely informative output. * * @param dimm pointer to already decoded @ref dimm_attr structure diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 3c433a931e..461fb65ea9 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -593,7 +593,7 @@ static void print_ns(const char *msg, u32 val) /** * \brief Print the info in DIMM * -* Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is +* Print info about the DIMM. Useful to use when CONFIG(DEBUG_RAM_SETUP) is * selected, or for a purely informative output. * * @param dimm pointer to already decoded @ref dimm_attr structure diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index ccb66cbeb5..e3d19180f0 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -24,7 +24,7 @@ void fsp_verify_memory_init_hobs(void); void fsp_print_header_info(const struct fsp_header *hdr); /* Callbacks for displaying UPD parameters - place in a separate file - * that is conditionally build with CONFIG_DISPLAY_UPD_DATA. + * that is conditionally build with CONFIG(DISPLAY_UPD_DATA). */ void soc_display_fspm_upd_params(const FSPM_UPD *fspm_old_upd, const FSPM_UPD *fspm_new_upd); @@ -32,7 +32,7 @@ void soc_display_fsps_upd_params(const FSPS_UPD *fsps_old_upd, const FSPS_UPD *fsps_new_upd); /* Callbacks for displaying HOBs - place in a separate file that is - * conditionally build with CONFIG_DISPLAY_HOBS. + * conditionally build with CONFIG(DISPLAY_HOBS). */ const char *soc_get_hob_type_name(const struct hob_header *hob); const char *soc_get_guid_name(const uint8_t *guid); diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 3227510941..d58a9993da 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -144,7 +144,7 @@ static void cmos_init_vbnv(bool invalid) uint8_t vbnv[VBOOT_VBNV_BLOCK_SIZE]; /* __cmos_init() will clear vbnv contents when a known rtc failure - occurred with !CONFIG_USE_OPTION_TABLE. However, __cmos_init() may + occurred with !CONFIG(USE_OPTION_TABLE). However, __cmos_init() may clear vbnv data for other internal reasons. For that, always back up the vbnv contents and conditionally save them when __cmos_init() indicates CMOS was cleared. */ diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 24851d1c86..7dd4397fdc 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -41,7 +41,7 @@ static struct spi_slave spi_slave; static struct tpm2_info tpm_info; /* - * TODO(vbendeb): make CONFIG_DEBUG_TPM an int to allow different level of + * TODO(vbendeb): make CONFIG(DEBUG_TPM) an int to allow different level of * debug traces. Right now it is either 0 or 1. */ static const int debug_level_ = CONFIG_DEBUG_TPM; diff --git a/src/ec/google/wilco/bootblock.h b/src/ec/google/wilco/bootblock.h index 2db8cfe4ab..8a5b69c34c 100644 --- a/src/ec/google/wilco/bootblock.h +++ b/src/ec/google/wilco/bootblock.h @@ -9,7 +9,7 @@ * This function performs early initialization of the EC: * * - Enable EC UART passthru for COM1 if serial console support - * is enabled with CONFIG_DRIVERS_UART_8250IO. + * is enabled with CONFIG(DRIVERS_UART_8250IO). */ void wilco_ec_early_init(void); diff --git a/src/ec/lenovo/h8/vboot.c b/src/ec/lenovo/h8/vboot.c index 97abb9de24..b564153331 100644 --- a/src/ec/lenovo/h8/vboot.c +++ b/src/ec/lenovo/h8/vboot.c @@ -33,7 +33,7 @@ int get_recovery_mode_switch(void) } /** - * Only used if CONFIG_CHROMEOS is set. + * Only used if CONFIG(CHROMEOS) is set. * Always zero as the #WP pin of the flash is tied high. */ int get_write_protect_state(void) diff --git a/src/include/device/dram/common.h b/src/include/device/dram/common.h index c1b4f7621b..9475853924 100644 --- a/src/include/device/dram/common.h +++ b/src/include/device/dram/common.h @@ -33,10 +33,10 @@ /** @} */ /** - * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP + * \brief Convenience macro for enabling printk with CONFIG(DEBUG_RAM_SETUP) * * Use this macro instead of printk(); for verbose RAM initialization messages. - * When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically + * When CONFIG(DEBUG_RAM_SETUP) is not selected, these messages are automatically * disabled. * @{ */ diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index a209e48b8b..74e0ff55f1 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -34,10 +34,10 @@ /** @} */ /** - * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP + * \brief Convenience macro for enabling printk with CONFIG(DEBUG_RAM_SETUP) * * Use this macro instead of printk(); for verbose RAM initialization messages. - * When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically + * When CONFIG(DEBUG_RAM_SETUP) is not selected, these messages are automatically * disabled. * @{ */ diff --git a/src/include/mrc_cache.h b/src/include/mrc_cache.h index 5131cbccd2..1cefba9da7 100644 --- a/src/include/mrc_cache.h +++ b/src/include/mrc_cache.h @@ -14,7 +14,7 @@ enum { /* * It's up to the caller to decide when to retrieve and stash data. There is - * differentiation on recovery mode CONFIG_HAS_RECOVERY_MRC_CACHE, but that's + * differentiation on recovery mode CONFIG(HAS_RECOVERY_MRC_CACHE), but that's * only for locating where to retrieve and save the data. If a platform doesn't * want to update the data then it shouldn't stash the data for saving. * Similarly, if the platform doesn't need the data for booting because of a diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 35b02dbb3d..1061e9905e 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -202,7 +202,7 @@ int chipset_volatile_group_begin(const struct spi_flash *flash); int chipset_volatile_group_end(const struct spi_flash *flash); /* Return spi_flash object reference for the boot device. This is only valid - * if CONFIG_BOOT_DEVICE_SPI_FLASH is enabled. */ + * if CONFIG(BOOT_DEVICE_SPI_FLASH) is enabled. */ const struct spi_flash *boot_device_spi_flash(void); /* Protect a region of spi flash using its controller, if available. Returns diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index fafa03b45d..efb3a4f7e1 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -16,12 +16,12 @@ static void bootblock_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to + * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/mainboard/intel/harcuvar/romstage.c b/src/mainboard/intel/harcuvar/romstage.c index fbad79836f..0373c01c60 100644 --- a/src/mainboard/intel/harcuvar/romstage.c +++ b/src/mainboard/intel/harcuvar/romstage.c @@ -12,7 +12,7 @@ /* * Define platform specific Memory Down Configure structure. * - * If CONFIG_ENABLE_FSP_MEMORY_DOWN is enabled, the MEMORY_DOWN_CONFIG + * If CONFIG(ENABLE_FSP_MEMORY_DOWN) is enabled, the MEMORY_DOWN_CONFIG * structure should be customized to match the design. * * .SlotState indicates the memory down state of the specific channel/DIMM. diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index e74354ebdb..a0e8fc0631 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -11,12 +11,12 @@ void bootblock_early_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to + * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 41f18be337..59c31aa672 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -10,11 +10,11 @@ void bootblock_early_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to setup the PCIEXBAR - * because CONFIG_MMCONF_SUPPORT is set to true. That way, all subsequent + * because CONFIG(MMCONF_SUPPORT) is set to true. That way, all subsequent * non-explicit config accesses use MCFG. This code also assumes that * bootblock_northbridge_init() is the first thing called in the non-asm * boot block code. The final assumption is that no assembly code is using - * the CONFIG_MMCONF_SUPPORT option to do PCI config acceses. + * the CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index 9d06120ecb..60051babd3 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -10,10 +10,10 @@ void bootblock_early_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to setup the PCIEXBAR - * because CONFIG_MMCONF_SUPPORT is set to true. That way all subsequent non-explicit + * because CONFIG(MMCONF_SUPPORT) is set to true. That way all subsequent non-explicit * config accesses use MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final assumption is that - * no assembly code is using the CONFIG_MMCONF_SUPPORT option to do PCI config accesses. + * no assembly code is using the CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 37ef02531e..dad61f9ee8 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -10,11 +10,11 @@ void bootblock_early_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to setup the - * PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to to true. That way, all + * PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to to true. That way, all * subsequent non-explicit config accesses use MCFG. This code also assumes * that bootblock_northbridge_init() is the first thing called in the non-asm * boot block code. The final assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ diff --git a/src/security/vboot/vboot_lib.c b/src/security/vboot/vboot_lib.c index 3ff1523c41..06fd6d7478 100644 --- a/src/security/vboot/vboot_lib.c +++ b/src/security/vboot/vboot_lib.c @@ -6,8 +6,8 @@ /* * vboot callbacks implemented by coreboot -- necessary for making general API - * calls when CONFIG_VBOOT_LIB is enabled. For callbacks specific to verstage - * (CONFIG_VBOOT), please see vboot_logic.c. + * calls when CONFIG(VBOOT_LIB) is enabled. For callbacks specific to verstage + * CONFIG(VBOOT), please see vboot_logic.c. */ void vb2ex_printf(const char *func, const char *fmt, ...) diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c index ef55699df3..5edfaeecaf 100644 --- a/src/soc/intel/broadwell/bootblock/systemagent.c +++ b/src/soc/intel/broadwell/bootblock/systemagent.c @@ -11,12 +11,12 @@ void bootblock_early_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to + * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 72d611a2cc..e12e07c376 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -226,7 +226,7 @@ static void imr_resource(struct device *dev, int idx, uint32_t base, /* * Add IMR ranges that hang off the host bridge/memory - * controller device in case CONFIG_SA_ENABLE_IMR is selected by SoC. + * controller device in case CONFIG(SA_ENABLE_IMR) is selected by SoC. */ static void sa_add_imr_resources(struct device *dev, int *resource_cnt) { diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h index a7823c347c..149e9b6ace 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_def.h +++ b/src/soc/intel/common/block/systemagent/systemagent_def.h @@ -40,7 +40,7 @@ #define MCH_PAIR 0x5418 /* - * IMR register in case CONFIG_SA_ENABLE_IMR is selected by SoC. + * IMR register in case CONFIG(SA_ENABLE_IMR) is selected by SoC. * * IMR registers are found under MCHBAR. */ |