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-rw-r--r--src/northbridge/intel/haswell/gma.c2
-rw-r--r--src/northbridge/intel/haswell/ram_calc.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 1c7aff9ea5..04fa6dacae 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -93,7 +93,7 @@ static const struct gt_reg haswell_gt_lock[] = {
/* some vga option roms are used for several chipsets but they only have one
* PCI ID in their header. If we encounter such an option rom, we need to do
- * the mapping ourselfes
+ * the mapping ourselves
*/
u32 map_oprom_vendev(u32 vendev)
diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c
index d51692c758..d3e88f2f84 100644
--- a/src/northbridge/intel/haswell/ram_calc.c
+++ b/src/northbridge/intel/haswell/ram_calc.c
@@ -24,7 +24,7 @@ static uintptr_t smm_region_start(void)
{
/*
* Base of TSEG is top of usable DRAM below 4GiB. The register has
- * 1 MiB alignement.
+ * 1 MiB alignment.
*/
uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
return tom & ~((1 << 20) - 1);