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-rw-r--r--src/northbridge/amd/lx/northbridgeinit.c2
-rw-r--r--src/northbridge/amd/lx/raminit.c5
2 files changed, 3 insertions, 4 deletions
diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c
index a07a1eacad..f385770bc7 100644
--- a/src/northbridge/amd/lx/northbridgeinit.c
+++ b/src/northbridge/amd/lx/northbridgeinit.c
@@ -738,7 +738,7 @@ void northbridge_init_early(void)
/* Now that the descriptor to memory is set up. */
/* The memory controller needs one read to synch its lines before it can be used. */
- i = *(volatile int *)0;
+ read32(zeroptr);
GeodeLinkPriority();
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index f20aed298a..c540f9a399 100644
--- a/src/northbridge/amd/lx/raminit.c
+++ b/src/northbridge/amd/lx/raminit.c
@@ -18,6 +18,7 @@
#include <cpu/amd/lxdef.h>
#include <arch/io.h>
#include <spd.h>
+#include <stddef.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include "raminit.h"
#include "northbridge.h"
@@ -747,10 +748,8 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* The RAM dll needs a write to lock on so generate a few dummy writes */
/* Note: The descriptor needs to be enabled to point at memory */
- volatile unsigned long *ptr;
for (i = 0; i < 5; i++) {
- ptr = (void *)i;
- *ptr = (unsigned long)i;
+ write32(zeroptr + i, i);
}
/* SWAPSiF for PBZ 4112 (Errata 34) */
/* check for failed DLL settings now that we have done a memory write. */