aboutsummaryrefslogtreecommitdiff
path: root/src/northbridge/amd/lx
diff options
context:
space:
mode:
authorPatrick Georgi <pgeorgi@chromium.org>2016-04-13 21:00:12 +0200
committerMartin Roth <martinroth@google.com>2016-04-16 01:50:55 +0200
commit59493717ad7aee5e4d6179b00c66b21af79e0376 (patch)
treed3c9c27408c0499e4876fe366d695e6ecdec4842 /src/northbridge/amd/lx
parentfab8ae77cb1a0fc078a4ddced50b3d30dec1df85 (diff)
northbridge/amd/{lx,gx2}: remove immediate accesses of 0
gcc doesn't like these because they're undefined behavior, so use zeroptr instead. For the loop that just does a number of writes (0..4), use zeroptr + i. Checked the disassembly (AMD_RUMBA and PCENGINES_ALIX2D) to not contain ud2 anymore and to look reasonable where zeroptr was used. Change-Id: I4a58220ec9a10c465909ca4ecbe5366d0a8cc0df Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14345 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/amd/lx')
-rw-r--r--src/northbridge/amd/lx/northbridgeinit.c2
-rw-r--r--src/northbridge/amd/lx/raminit.c5
2 files changed, 3 insertions, 4 deletions
diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c
index a07a1eacad..f385770bc7 100644
--- a/src/northbridge/amd/lx/northbridgeinit.c
+++ b/src/northbridge/amd/lx/northbridgeinit.c
@@ -738,7 +738,7 @@ void northbridge_init_early(void)
/* Now that the descriptor to memory is set up. */
/* The memory controller needs one read to synch its lines before it can be used. */
- i = *(volatile int *)0;
+ read32(zeroptr);
GeodeLinkPriority();
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index f20aed298a..c540f9a399 100644
--- a/src/northbridge/amd/lx/raminit.c
+++ b/src/northbridge/amd/lx/raminit.c
@@ -18,6 +18,7 @@
#include <cpu/amd/lxdef.h>
#include <arch/io.h>
#include <spd.h>
+#include <stddef.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include "raminit.h"
#include "northbridge.h"
@@ -747,10 +748,8 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* The RAM dll needs a write to lock on so generate a few dummy writes */
/* Note: The descriptor needs to be enabled to point at memory */
- volatile unsigned long *ptr;
for (i = 0; i < 5; i++) {
- ptr = (void *)i;
- *ptr = (unsigned long)i;
+ write32(zeroptr + i, i);
}
/* SWAPSiF for PBZ 4112 (Errata 34) */
/* check for failed DLL settings now that we have done a memory write. */