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path: root/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c
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Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctwl.c')
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctwl.c16
1 files changed, 15 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c
index 57d56814c1..2e749f8cd4 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c
@@ -342,7 +342,21 @@ void SetTargetFreq(struct MCTStatStruc *pMCTstat,
mct_Wait(250);
if (pDCTstat->Status & (1 << SB_Registered)) {
- /* TODO: Assuming the dct==0. The agesa here is confusing. */
+ u8 DCT0Present, DCT1Present;
+
+ DCT0Present = pDCTstat->DIMMValidDCT[0];
+ if (pDCTstat->GangedMode)
+ DCT1Present = 0;
+ else
+ DCT1Present = pDCTstat->DIMMValidDCT[1];
+
+ if (!DCT1Present)
+ pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[0];
+ else if (pDCTstat->GangedMode) {
+ pDCTstat->CSPresent = 0;
+ } else
+ pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[1];
+
FreqChgCtrlWrd(pMCTstat, pDCTstat);
}
}