diff options
| author | Zheng Bao <zheng.bao@amd.com> | 2011-01-17 02:20:33 +0000 |
|---|---|---|
| committer | Zheng Bao <Zheng.Bao@amd.com> | 2011-01-17 02:20:33 +0000 |
| commit | a7296e74f1c1bd33f2c19c498443955d674cfacb (patch) | |
| tree | 75a93363813da5aeaad9951a474bda133a7786fe /src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | |
| parent | a1125235ecc8c6ff9df1fd293de273111774345a (diff) | |
The code is tested on my board with register DIMMs. More tests need to be
done. Please send the testing report.
Note: The pDCTstat->PresetmaxFreq in mctGet_MaxLoadFreq() should be set
to a higher limit, otherwise the frequnce will be set as 400MHz.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Scott Duplichan <scott@notabs.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctwl.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c index 57d56814c1..2e749f8cd4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c @@ -342,7 +342,21 @@ void SetTargetFreq(struct MCTStatStruc *pMCTstat, mct_Wait(250); if (pDCTstat->Status & (1 << SB_Registered)) { - /* TODO: Assuming the dct==0. The agesa here is confusing. */ + u8 DCT0Present, DCT1Present; + + DCT0Present = pDCTstat->DIMMValidDCT[0]; + if (pDCTstat->GangedMode) + DCT1Present = 0; + else + DCT1Present = pDCTstat->DIMMValidDCT[1]; + + if (!DCT1Present) + pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[0]; + else if (pDCTstat->GangedMode) { + pDCTstat->CSPresent = 0; + } else + pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[1]; + FreqChgCtrlWrd(pMCTstat, pDCTstat); } } |