4 files changed, 84 insertions, 1 deletions
diff --git a/src/mainboard/amd/gardenia/Makefile.inc b/src/mainboard/amd/gardenia/Makefile.inc
index 4c637bbfbf..cceb84c48e 100644
--- a/src/mainboard/amd/gardenia/Makefile.inc
+++ b/src/mainboard/amd/gardenia/Makefile.inc
@@ -13,12 +13,13 @@
 # GNU General Public License for more details.
 #
 
-bootblock-y += bootblock/BiosCallOuts.c
+bootblock-y += bootblock/gpio.c
 bootblock-y += bootblock/OemCustomize.c
 
 romstage-y += BiosCallOuts.c
 romstage-y += OemCustomize.c
 
+ramstage-y += bootblock/gpio.c
 ramstage-y += BiosCallOuts.c
 ramstage-y += OemCustomize.c
 ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += fchec.c
diff --git a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c b/src/mainboard/amd/gardenia/bootblock/gpio.c
index 7e60daee27..7b18618465 100644
--- a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c
+++ b/src/mainboard/amd/gardenia/bootblock/gpio.c
@@ -17,6 +17,22 @@
 #include <amdblocks/BiosCallOuts.h>
 #include <soc/southbridge.h>
 #include <stdlib.h>
+#include <soc/gpio.h>
+
+/*
+ * As a rule of thumb, GPIO pins used by coreboot should be initialized at
+ * bootblock while GPIO pins used only by the OS should be initialized at
+ * ramstage.
+ */
+const struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = {
+	/* NFC PU */
+	{GPIO_64, Function0, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H },
+};
+
+const struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = {
+	/* BT radio disable */
+	{GPIO_14, Function1, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H },
+};
 
 static const GPIO_CONTROL oem_gardenia_gpio[] = {
 	/* BT radio disable */
@@ -48,3 +64,13 @@ void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset)
 {
 	FchParams_reset->EarlyOemGpioTable = (void *)oem_gardenia_gpio;
 }
+
+const struct soc_amd_stoneyridge_gpio *board_get_gpio(size_t *size)
+{
+	if (GPIO_TABLE_BOOTBLOCK) {
+		*size = ARRAY_SIZE(gpio_set_stage_reset);
+		return gpio_set_stage_reset;
+	}
+	*size = ARRAY_SIZE(gpio_set_stage_ram);
+	return gpio_set_stage_ram;
+}
diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
index 58d9473218..0566320e80 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
@@ -23,6 +23,26 @@
 /*
  * These settings were generated by a spreadsheet. If they need to be updated,
  * update the spreadsheet shared with the Grunt development team.
+ *
+ * As a rule of thumb, GPIO pins used by coreboot should be initialized at
+ * bootblock while GPIO pins used only by the OS should be initialized at
+ * ramstage.
+ */
+const static struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = {
+
+	/* GPIO_0 - EC_PCH_PWR_BTN_ODL */
+	{ GPIO_0, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT },
+};
+
+const static struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = {
+
+	/* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL */
+	{ GPIO_2, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT },
+};
+
+/*
+ * These settings were generated by a spreadsheet. If they need to be updated,
+ * update the spreadsheet shared with the Grunt development team.
  */
 static const GPIO_CONTROL agesa_board_gpios[] = {
 
@@ -260,6 +280,17 @@ const __attribute__((weak)) GPIO_CONTROL *get_gpio_table(void)
 	return agesa_board_gpios;
 }
 
+const __attribute__((weak)) const struct soc_amd_stoneyridge_gpio
+					*board_get_gpio(size_t *size)
+{
+	if (GPIO_TABLE_BOOTBLOCK) {
+		*size = ARRAY_SIZE(gpio_set_stage_reset);
+		return gpio_set_stage_reset;
+	}
+	*size = ARRAY_SIZE(gpio_set_stage_ram);
+	return gpio_set_stage_ram;
+}
+
 /*
  * GPE setup table must match ACPI GPE ASL
  *  { gevent, gpe, direction, level }
diff --git a/src/mainboard/google/kahlee/variants/kahlee/gpio.c b/src/mainboard/google/kahlee/variants/kahlee/gpio.c
index e5e15e610d..dda44afe7e 100644
--- a/src/mainboard/google/kahlee/variants/kahlee/gpio.c
+++ b/src/mainboard/google/kahlee/variants/kahlee/gpio.c
@@ -20,6 +20,21 @@
 #include <stdlib.h>
 #include <variant/gpio.h>
 
+/*
+ * As a rule of thumb, GPIO pins used by coreboot should be initialized at
+ * bootblock while GPIO pins used only by the OS should be initialized at
+ * ramstage.
+ */
+const struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = {
+	/* AGPIO2, to become event generator */
+	{ GPIO_2, Function1, FCH_GPIO_PULL_UP_ENABLE | INPUT },
+};
+
+const struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = {
+	/* AGPIO 12 */
+	{ GPIO_12, Function2, FCH_GPIO_PULL_UP_ENABLE | INPUT },
+};
+
 static const GPIO_CONTROL agesa_board_gpios[] = {
 	/* AGPIO2 PCIE/WLAN WAKE# SCI*/
 	{2, Function1, FCH_GPIO_PULL_UP_ENABLE },
@@ -104,6 +119,16 @@ const GPIO_CONTROL *get_gpio_table(void)
 	return agesa_board_gpios;
 }
 
+const struct soc_amd_stoneyridge_gpio *board_get_gpio(size_t *size)
+{
+	if (GPIO_TABLE_BOOTBLOCK) {
+		*size = ARRAY_SIZE(gpio_set_stage_reset);
+		return gpio_set_stage_reset;
+	}
+	*size = ARRAY_SIZE(gpio_set_stage_ram);
+	return gpio_set_stage_ram;
+}
+
 /*
  * GPE setup table must match ACPI GPE ASL
  *  { gevent, gpe, direction, level }