diff options
Diffstat (limited to 'src/mainboard/google/kahlee/variants/baseboard/gpio.c')
-rw-r--r-- | src/mainboard/google/kahlee/variants/baseboard/gpio.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 58d9473218..0566320e80 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -23,6 +23,26 @@ /* * These settings were generated by a spreadsheet. If they need to be updated, * update the spreadsheet shared with the Grunt development team. + * + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +const static struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = { + + /* GPIO_0 - EC_PCH_PWR_BTN_ODL */ + { GPIO_0, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, +}; + +const static struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = { + + /* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL */ + { GPIO_2, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, +}; + +/* + * These settings were generated by a spreadsheet. If they need to be updated, + * update the spreadsheet shared with the Grunt development team. */ static const GPIO_CONTROL agesa_board_gpios[] = { @@ -260,6 +280,17 @@ const __attribute__((weak)) GPIO_CONTROL *get_gpio_table(void) return agesa_board_gpios; } +const __attribute__((weak)) const struct soc_amd_stoneyridge_gpio + *board_get_gpio(size_t *size) +{ + if (GPIO_TABLE_BOOTBLOCK) { + *size = ARRAY_SIZE(gpio_set_stage_reset); + return gpio_set_stage_reset; + } + *size = ARRAY_SIZE(gpio_set_stage_ram); + return gpio_set_stage_ram; +} + /* * GPE setup table must match ACPI GPE ASL * { gevent, gpe, direction, level } |