diff options
Diffstat (limited to 'src/mainboard/tyan')
| -rw-r--r-- | src/mainboard/tyan/s2891/Config.lb | 55 | ||||
| -rw-r--r-- | src/mainboard/tyan/s2892/Config.lb | 56 | ||||
| -rw-r--r-- | src/mainboard/tyan/s2895/Config.lb | 57 | ||||
| -rw-r--r-- | src/mainboard/tyan/s4880/Config.lb | 64 | ||||
| -rw-r--r-- | src/mainboard/tyan/s4880/auto.c | 233 | ||||
| -rw-r--r-- | src/mainboard/tyan/s4880/failover.c | 69 | ||||
| -rw-r--r-- | src/mainboard/tyan/s4882/Config.lb | 64 | ||||
| -rw-r--r-- | src/mainboard/tyan/s4882/auto.c | 233 | ||||
| -rw-r--r-- | src/mainboard/tyan/s4882/failover.c | 68 |
9 files changed, 0 insertions, 899 deletions
diff --git a/src/mainboard/tyan/s2891/Config.lb b/src/mainboard/tyan/s2891/Config.lb index e7a8ac3850..1131c3d3f2 100644 --- a/src/mainboard/tyan/s2891/Config.lb +++ b/src/mainboard/tyan/s2891/Config.lb @@ -63,8 +63,6 @@ if HAVE_ACPI_TABLES #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb end -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -79,32 +77,6 @@ else end end -else - ## - ## Romcc output - ## - makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" - end - - makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" - end - - makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" - end - - makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" - end - -end - ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -115,7 +87,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -123,7 +94,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -136,12 +106,6 @@ else ldscript /cpu/x86/32bit/reset32.lds end -if USE_DCACHE_RAM -else - ### Should this be in the northbridge code? - mainboardinit arch/i386/lib/cpu_reset.inc -end - ## ## Include an id string (For safe flashing) ## @@ -156,12 +120,10 @@ if USE_FALLBACK_IMAGE ldscript /southbridge/nvidia/ck804/romstrap.lds end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -170,10 +132,6 @@ end ### if USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds - if USE_DCACHE_RAM - else - mainboardinit ./failover.inc - end end ### @@ -183,25 +141,12 @@ end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -else - # ROMCC - mainboardinit cpu/x86/fpu/enable_fpu.inc - mainboardinit cpu/x86/mmx/enable_mmx.inc - mainboardinit cpu/x86/sse/enable_sse.inc - mainboardinit ./auto.inc - mainboardinit cpu/x86/sse/disable_sse.inc - mainboardinit cpu/x86/mmx/disable_mmx.inc - -end - ## ## Include the secondary Configuration files ## diff --git a/src/mainboard/tyan/s2892/Config.lb b/src/mainboard/tyan/s2892/Config.lb index bcc444d1a6..e02d732875 100644 --- a/src/mainboard/tyan/s2892/Config.lb +++ b/src/mainboard/tyan/s2892/Config.lb @@ -63,8 +63,6 @@ if HAVE_ACPI_TABLES #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb end -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -79,32 +77,6 @@ else end end -else - ## - ## Romcc output - ## - makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" - end - - makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" - end - - makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" - end - - makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" - end - -end - ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -115,7 +87,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -123,7 +94,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -136,12 +106,6 @@ else ldscript /cpu/x86/32bit/reset32.lds end -if USE_DCACHE_RAM -else - ### Should this be in the northbridge code? - mainboardinit arch/i386/lib/cpu_reset.inc -end - ## ## Include an id string (For safe flashing) ## @@ -156,12 +120,10 @@ if USE_FALLBACK_IMAGE ldscript /southbridge/nvidia/ck804/romstrap.lds end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -169,12 +131,7 @@ end ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM - ldscript /arch/i386/lib/failover.lds - else ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc - end end ### @@ -184,25 +141,12 @@ end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -else - # ROMCC - mainboardinit cpu/x86/fpu/enable_fpu.inc - mainboardinit cpu/x86/mmx/enable_mmx.inc - mainboardinit cpu/x86/sse/enable_sse.inc - mainboardinit ./auto.inc - mainboardinit cpu/x86/sse/disable_sse.inc - mainboardinit cpu/x86/mmx/disable_mmx.inc - -end - ## ## Include the secondary Configuration files ## diff --git a/src/mainboard/tyan/s2895/Config.lb b/src/mainboard/tyan/s2895/Config.lb index bc5007506f..8bbacfc026 100644 --- a/src/mainboard/tyan/s2895/Config.lb +++ b/src/mainboard/tyan/s2895/Config.lb @@ -72,8 +72,6 @@ if HAVE_ACPI_TABLES #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb end -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -88,32 +86,6 @@ else end end -else - ## - ## Romcc output - ## - makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" - end - - makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" - end - - makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" - end - - makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" - end - -end - ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -131,7 +103,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -139,7 +110,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -162,12 +132,6 @@ else end end -if USE_DCACHE_RAM -else - ### Should this be in the northbridge code? - mainboardinit arch/i386/lib/cpu_reset.inc -end - ## ## Include an id string (For safe flashing) ## @@ -189,12 +153,10 @@ else end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -203,42 +165,23 @@ end ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - else - mainboardinit ./failover.inc - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -else - # ROMCC - mainboardinit cpu/x86/fpu/enable_fpu.inc - mainboardinit cpu/x86/mmx/enable_mmx.inc - mainboardinit cpu/x86/sse/enable_sse.inc - mainboardinit ./auto.inc - mainboardinit cpu/x86/sse/disable_sse.inc - mainboardinit cpu/x86/mmx/disable_mmx.inc - -end - ## ## Include the secondary Configuration files ## diff --git a/src/mainboard/tyan/s4880/Config.lb b/src/mainboard/tyan/s4880/Config.lb index cf728b82ad..ac36e925a7 100644 --- a/src/mainboard/tyan/s4880/Config.lb +++ b/src/mainboard/tyan/s4880/Config.lb @@ -43,7 +43,6 @@ arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -if USE_DCACHE_RAM if CONFIG_USE_INIT @@ -61,43 +60,6 @@ if USE_DCACHE_RAM action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -else - - ## - ## Romcc output - ## - makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" - end - - makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" - end - - makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" - end - - makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" - end - - ## - ## Setup RAM - ## - mainboardinit cpu/x86/fpu/enable_fpu.inc - mainboardinit cpu/x86/mmx/enable_mmx.inc - mainboardinit cpu/x86/sse/enable_sse.inc - mainboardinit ./auto.inc - mainboardinit cpu/x86/sse/disable_sse.inc - mainboardinit cpu/x86/mmx/disable_mmx.inc - mainboardinit arch/i386/lib/jmp_auto_out.inc - -end ## ## Build our 16 bit and 32 bit coreboot entry code @@ -109,7 +71,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -117,8 +78,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) @@ -131,25 +90,16 @@ else ldscript /cpu/x86/32bit/reset32.lds end -if USE_DCACHE_RAM -else - ### Should this be in the northbridge code? - mainboardinit arch/i386/lib/cpu_reset.inc -end - ## ## Include an id string (For safe flashing) ## mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds - -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -157,32 +107,18 @@ end ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - else - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc - end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -else - - # ROMCC - mainboardinit arch/i386/lib/jmp_auto.inc - -end - ## ## Include the secondary Configuration files ## diff --git a/src/mainboard/tyan/s4880/auto.c b/src/mainboard/tyan/s4880/auto.c index 36115f6a0d..e69de29bb2 100644 --- a/src/mainboard/tyan/s4880/auto.c +++ b/src/mainboard/tyan/s4880/auto.c @@ -1,233 +0,0 @@ -#define ASSEMBLY 1 - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <arch/romcc_io.h> -#include <cpu/x86/lapic.h> -#include <arch/cpu.h> -#include <stdlib.h> -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" -#include "ram/ramtest.c" -#include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/amd/amd8111/amd8111_early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" -#include "lib/delay.c" -#include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" -#include <cpu/amd/model_fxx_rev.h> -#include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" -#include "cpu/x86/bist.h" -#include "cpu/amd/dualcore/dualcore.c" - -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) - -/* Look up a which bus a given node/link combination is on. - * return 0 when we can't find the answer. - */ -static unsigned node_link_to_bus(unsigned node, unsigned link) -{ - unsigned reg; - - for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - unsigned config_map; - config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); - if ((config_map & 3) != 3) { - continue; - } - if ((((config_map >> 4) & 7) == node) && - (((config_map >> 8) & 3) == link)) - { - return (config_map >> 16) & 0xff; - } - } - return 0; -} - -static void hard_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3); - - set_bios_reset(); - - /* enable cf9 */ - pci_write_config8(dev, 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0); - - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); -} - -static void memreset_setup(void) -{ - if (is_cpu_pre_c0()) { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 - } - else { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 - } - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ - if (is_cpu_pre_c0()) { - udelay(800); - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 - udelay(90); - } -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ -#define SMBUS_HUB 0x18 - unsigned device=(ctrl->channel0[0])>>8; - smbus_write_byte(SMBUS_HUB , 0x01, device); - smbus_write_byte(SMBUS_HUB , 0x03, 0); -} -#if 0 -static inline void change_i2c_mux(unsigned device) -{ -#define SMBUS_HUB 0x18 - smbus_write_byte(SMBUS_HUB , 0x01, device); - smbus_write_byte(SMBUS_HUB , 0x03, 0); -} -#endif - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/amd/amdk8/setup_resource_map.c" -#include "northbridge/amd/amdk8/raminit.c" - -#include "northbridge/amd/amdk8/coherent_ht.c" -#include "sdram/generic_sdram.c" - - /* tyan does not want the default */ -#include "resourcemap.c" - -#define FIRST_CPU 1 -#define SECOND_CPU 1 - -#define THIRD_CPU 1 -#define FOURTH_CPU 1 - -#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU + THIRD_CPU + FOURTH_CPU) - -#define RC0 ((1<<1)<<8) -#define RC1 ((1<<2)<<8) -#define RC2 ((1<<3)<<8) -#define RC3 ((1<<4)<<8) - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 - -static void main(unsigned long bist) -{ - static const struct mem_controller cpu[] = { -#if FIRST_CPU - { - .node_id = 0, - .f0 = PCI_DEV(0, 0x18, 0), - .f1 = PCI_DEV(0, 0x18, 1), - .f2 = PCI_DEV(0, 0x18, 2), - .f3 = PCI_DEV(0, 0x18, 3), - .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 }, - .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 }, - }, -#endif -#if SECOND_CPU - { - .node_id = 1, - .f0 = PCI_DEV(0, 0x19, 0), - .f1 = PCI_DEV(0, 0x19, 1), - .f2 = PCI_DEV(0, 0x19, 2), - .f3 = PCI_DEV(0, 0x19, 3), - .channel0 = { RC1|DIMM0, 0 , 0, 0 }, - .channel1 = { RC1|DIMM1, 0, 0, 0 }, - - }, -#endif - -#if THIRD_CPU - { - .node_id = 2, - .f0 = PCI_DEV(0, 0x1a, 0), - .f1 = PCI_DEV(0, 0x1a, 1), - .f2 = PCI_DEV(0, 0x1a, 2), - .f3 = PCI_DEV(0, 0x1a, 3), - .channel0 = { RC2|DIMM0, 0, 0, 0 }, - .channel1 = { RC2|DIMM1, 0, 0, 0 }, - - }, -#endif -#if FOURTH_CPU - { - .node_id = 3, - .f0 = PCI_DEV(0, 0x1b, 0), - .f1 = PCI_DEV(0, 0x1b, 1), - .f2 = PCI_DEV(0, 0x1b, 2), - .f3 = PCI_DEV(0, 0x1b, 3), - .channel0 = { RC3|DIMM0, 0, 0, 0 }, - .channel1 = { RC3|DIMM1, 0, 0, 0 }, - - }, -#endif - }; - int i; - int needs_reset; - - if (bist == 0) { - k8_init_and_stop_secondaries(); - } - - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); - uart_init(); - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - setup_s4880_resource_map(); - - needs_reset = setup_coherent_ht_domain(); - - needs_reset |= ht_setup_chains_x(); - - if (needs_reset) { - print_info("ht reset -\r\n"); - soft_reset(); - } - -#if 0 - dump_pci_devices(); -#endif - enable_smbus(); - - memreset_setup(); - sdram_initialize(ARRAY_SIZE(cpu), cpu); - -} diff --git a/src/mainboard/tyan/s4880/failover.c b/src/mainboard/tyan/s4880/failover.c index c347af32dd..e69de29bb2 100644 --- a/src/mainboard/tyan/s4880/failover.c +++ b/src/mainboard/tyan/s4880/failover.c @@ -1,69 +0,0 @@ -#define ASSEMBLY 1 -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <arch/romcc_io.h> -#include <cpu/x86/lapic.h> -#include "pc80/mc146818rtc_early.c" -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" -#include "northbridge/amd/amdk8/early_ht.c" -#include "cpu/x86/lapic/boot_cpu.c" -#include "cpu/x86/mtrr/earlymtrr.c" -#include "northbridge/amd/amdk8/reset_test.c" - -#if CONFIG_LOGICAL_CPUS==1 -#include "cpu/amd/dualcore/dualcore_id.c" -#endif - - -static unsigned long main(unsigned long bist) -{ - /* Make cerain my local apic is useable */ - enable_lapic(); - - /* Is this a cpu only reset? */ - if (early_mtrr_init_detected()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto fallback_image; - } - } - /* Is this a secondary cpu? */ - if (!boot_cpu()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto fallback_image; - } - } - - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* Setup the 8111 */ - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: - return bist; -} diff --git a/src/mainboard/tyan/s4882/Config.lb b/src/mainboard/tyan/s4882/Config.lb index 88ae617cd7..d3e1bb509b 100644 --- a/src/mainboard/tyan/s4882/Config.lb +++ b/src/mainboard/tyan/s4882/Config.lb @@ -43,7 +43,6 @@ arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -if USE_DCACHE_RAM if CONFIG_USE_INIT @@ -61,43 +60,6 @@ if USE_DCACHE_RAM action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -else - - ## - ## Romcc output - ## - makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" - end - - makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" - end - - makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" - end - - makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" - end - - ## - ## Setup RAM - ## - mainboardinit cpu/x86/fpu/enable_fpu.inc - mainboardinit cpu/x86/mmx/enable_mmx.inc - mainboardinit cpu/x86/sse/enable_sse.inc - mainboardinit ./auto.inc - mainboardinit cpu/x86/sse/disable_sse.inc - mainboardinit cpu/x86/mmx/disable_mmx.inc - mainboardinit arch/i386/lib/jmp_auto_out.inc - -end ## ## Build our 16 bit and 32 bit coreboot entry code @@ -109,7 +71,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -117,8 +78,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) @@ -131,25 +90,16 @@ else ldscript /cpu/x86/32bit/reset32.lds end -if USE_DCACHE_RAM -else - ### Should this be in the northbridge code? - mainboardinit arch/i386/lib/cpu_reset.inc -end - ## ## Include an id string (For safe flashing) ## mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds - -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -157,32 +107,18 @@ end ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - else - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc - end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -else - - # ROMCC - mainboardinit arch/i386/lib/jmp_auto.inc - -end - ## ## Include the secondary Configuration files ## diff --git a/src/mainboard/tyan/s4882/auto.c b/src/mainboard/tyan/s4882/auto.c index 7576e4de26..e69de29bb2 100644 --- a/src/mainboard/tyan/s4882/auto.c +++ b/src/mainboard/tyan/s4882/auto.c @@ -1,233 +0,0 @@ -#define ASSEMBLY 1 - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <arch/romcc_io.h> -#include <cpu/x86/lapic.h> -#include <stdlib.h> -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" -#include "ram/ramtest.c" -#include "southbridge/amd/amd8111/amd8111_early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" -#include "lib/delay.c" -#include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" -#include "northbridge/amd/amdk8/incoherent_ht.c" -#include <cpu/amd/model_fxx_rev.h> -#include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" -#include "cpu/x86/bist.h" -#include "cpu/amd/dualcore/dualcore.c" - -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) - -/* Look up a which bus a given node/link combination is on. - * return 0 when we can't find the answer. - */ -static unsigned node_link_to_bus(unsigned node, unsigned link) -{ - unsigned reg; - - for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - unsigned config_map; - config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); - if ((config_map & 3) != 3) { - continue; - } - if ((((config_map >> 4) & 7) == node) && - (((config_map >> 8) & 3) == link)) - { - return (config_map >> 16) & 0xff; - } - } - return 0; -} - -static void hard_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 3); - - set_bios_reset(); - - /* enable cf9 */ - pci_write_config8(dev, 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 0); - - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); -} - -static void memreset_setup(void) -{ - if (is_cpu_pre_c0()) { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 - } - else { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 - } - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ - if (is_cpu_pre_c0()) { - udelay(800); - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 - udelay(90); - } -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ -#define SMBUS_HUB 0x18 - int ret,i; - unsigned device=(ctrl->channel0[0])>>8; - /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ - i=2; - do { - ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - } while ((ret!=0) && (i-->0)); - - smbus_write_byte(SMBUS_HUB, 0x03, 0); -} - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/amd/amdk8/setup_resource_map.c" -#define QRANK_DIMM_SUPPORT 1 -#include "northbridge/amd/amdk8/raminit.c" -#if 0 - #define ENABLE_APIC_EXT_ID 1 - #define APIC_ID_OFFSET 0x10 - #define LIFT_BSP_APIC_ID 0 -#else - #define ENABLE_APIC_EXT_ID 0 -#endif -#include "northbridge/amd/amdk8/coherent_ht.c" -#include "sdram/generic_sdram.c" - - /* tyan does not want the default */ -#include "resourcemap.c" - -#define FIRST_CPU 1 -#define SECOND_CPU 1 - -#define THIRD_CPU 1 -#define FOURTH_CPU 1 - -#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU + THIRD_CPU + FOURTH_CPU) - -#define RC0 ((1<<2)<<8) -#define RC1 ((1<<1)<<8) -#define RC2 ((1<<4)<<8) -#define RC3 ((1<<3)<<8) - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 - -static void main(unsigned long bist) -{ - static const struct mem_controller cpu[] = { -#if FIRST_CPU - { - .node_id = 0, - .f0 = PCI_DEV(0, 0x18, 0), - .f1 = PCI_DEV(0, 0x18, 1), - .f2 = PCI_DEV(0, 0x18, 2), - .f3 = PCI_DEV(0, 0x18, 3), - .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 }, - .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 }, - }, -#endif -#if SECOND_CPU - { - .node_id = 1, - .f0 = PCI_DEV(0, 0x19, 0), - .f1 = PCI_DEV(0, 0x19, 1), - .f2 = PCI_DEV(0, 0x19, 2), - .f3 = PCI_DEV(0, 0x19, 3), - .channel0 = { RC1|DIMM0, RC1|DIMM2 , 0, 0 }, - .channel1 = { RC1|DIMM1, RC1|DIMM3 , 0, 0 }, - - }, -#endif - -#if THIRD_CPU - { - .node_id = 2, - .f0 = PCI_DEV(0, 0x1a, 0), - .f1 = PCI_DEV(0, 0x1a, 1), - .f2 = PCI_DEV(0, 0x1a, 2), - .f3 = PCI_DEV(0, 0x1a, 3), - .channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 }, - .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 }, - - }, -#endif -#if FOURTH_CPU - { - .node_id = 3, - .f0 = PCI_DEV(0, 0x1b, 0), - .f1 = PCI_DEV(0, 0x1b, 1), - .f2 = PCI_DEV(0, 0x1b, 2), - .f3 = PCI_DEV(0, 0x1b, 3), - .channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 }, - .channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 }, - - }, -#endif - }; - int i; - int needs_reset; - - if (bist == 0) { - k8_init_and_stop_secondaries(); - } - - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); - uart_init(); - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - setup_s4882_resource_map(); - - needs_reset = setup_coherent_ht_domain(); - - needs_reset |= ht_setup_chains_x(); - if (needs_reset) { - print_info("ht reset -\r\n"); - soft_reset(); - } - - enable_smbus(); - - memreset_setup(); - sdram_initialize(ARRAY_SIZE(cpu), cpu); - -} diff --git a/src/mainboard/tyan/s4882/failover.c b/src/mainboard/tyan/s4882/failover.c index 77e9851410..e69de29bb2 100644 --- a/src/mainboard/tyan/s4882/failover.c +++ b/src/mainboard/tyan/s4882/failover.c @@ -1,68 +0,0 @@ -#define ASSEMBLY 1 -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <arch/romcc_io.h> -#include <cpu/x86/lapic.h> -#include "pc80/mc146818rtc_early.c" -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" -#include "northbridge/amd/amdk8/early_ht.c" -#include "cpu/x86/lapic/boot_cpu.c" -#include "cpu/x86/mtrr/earlymtrr.c" -#include "northbridge/amd/amdk8/reset_test.c" - -#if CONFIG_LOGICAL_CPUS==1 -#include "cpu/amd/dualcore/dualcore_id.c" -#else -#include "cpu/amd/model_fxx/node_id.c" -#endif - - -static unsigned long main(unsigned long bist) -{ - - /* Is this a cpu only reset? */ - if (early_mtrr_init_detected()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto fallback_image; - } - } - /* Is this a secondary cpu? */ - if (!boot_cpu()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* Setup the 8111 */ - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: - return bist; -} |