diff options
Diffstat (limited to 'src/mainboard/tyan/s4880/Config.lb')
| -rw-r--r-- | src/mainboard/tyan/s4880/Config.lb | 64 |
1 files changed, 0 insertions, 64 deletions
diff --git a/src/mainboard/tyan/s4880/Config.lb b/src/mainboard/tyan/s4880/Config.lb index cf728b82ad..ac36e925a7 100644 --- a/src/mainboard/tyan/s4880/Config.lb +++ b/src/mainboard/tyan/s4880/Config.lb @@ -43,7 +43,6 @@ arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -if USE_DCACHE_RAM if CONFIG_USE_INIT @@ -61,43 +60,6 @@ if USE_DCACHE_RAM action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -else - - ## - ## Romcc output - ## - makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" - end - - makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" - end - - makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" - end - - makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" - end - - ## - ## Setup RAM - ## - mainboardinit cpu/x86/fpu/enable_fpu.inc - mainboardinit cpu/x86/mmx/enable_mmx.inc - mainboardinit cpu/x86/sse/enable_sse.inc - mainboardinit ./auto.inc - mainboardinit cpu/x86/sse/disable_sse.inc - mainboardinit cpu/x86/mmx/disable_mmx.inc - mainboardinit arch/i386/lib/jmp_auto_out.inc - -end ## ## Build our 16 bit and 32 bit coreboot entry code @@ -109,7 +71,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -117,8 +78,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) @@ -131,25 +90,16 @@ else ldscript /cpu/x86/32bit/reset32.lds end -if USE_DCACHE_RAM -else - ### Should this be in the northbridge code? - mainboardinit arch/i386/lib/cpu_reset.inc -end - ## ## Include an id string (For safe flashing) ## mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds - -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -157,32 +107,18 @@ end ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - else - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc - end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -else - - # ROMCC - mainboardinit arch/i386/lib/jmp_auto.inc - -end - ## ## Include the secondary Configuration files ## |