diff options
Diffstat (limited to 'src/mainboard/starlabs/labtop/variants/kbl')
| -rw-r--r-- | src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/mainboard/starlabs/labtop/variants/kbl/board.fmd | 13 | ||||
| -rw-r--r-- | src/mainboard/starlabs/labtop/variants/kbl/data.vbt | bin | 6144 -> 0 bytes | |||
| -rw-r--r-- | src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb | 203 | ||||
| -rw-r--r-- | src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads | 18 | ||||
| -rw-r--r-- | src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h | 203 | ||||
| -rw-r--r-- | src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h | 77 | ||||
| -rw-r--r-- | src/mainboard/starlabs/labtop/variants/kbl/romstage.c | 36 |
8 files changed, 0 insertions, 554 deletions
diff --git a/src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc b/src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc deleted file mode 100644 index e04a8dba30..0000000000 --- a/src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR) - -romstage-y += romstage.c diff --git a/src/mainboard/starlabs/labtop/variants/kbl/board.fmd b/src/mainboard/starlabs/labtop/variants/kbl/board.fmd deleted file mode 100644 index 08bc519499..0000000000 --- a/src/mainboard/starlabs/labtop/variants/kbl/board.fmd +++ /dev/null @@ -1,13 +0,0 @@ -# -# Manually defined FMD in order to ensure that space is reserved for the EC -# at the top of the BIOS region. -# -FLASH 8M { - BIOS@0x200000 0x600000 { - RW_MRC_CACHE@0x0 0x10000 - SMMSTORE@0x10000 0x40000 - CONSOLE@0x50000 0x20000 - FMAP@0x70000 0x200 - COREBOOT(CBFS) - } -} diff --git a/src/mainboard/starlabs/labtop/variants/kbl/data.vbt b/src/mainboard/starlabs/labtop/variants/kbl/data.vbt Binary files differdeleted file mode 100644 index b7146c52ec..0000000000 --- a/src/mainboard/starlabs/labtop/variants/kbl/data.vbt +++ /dev/null diff --git a/src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb deleted file mode 100644 index d052352cea..0000000000 --- a/src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb +++ /dev/null @@ -1,203 +0,0 @@ -chip soc/intel/skylake - # Disable DEEP - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "0" - register "deep_s5_enable_dc" = "0" - register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" - - # Enable "Intel Speed Shift Technology" - register "eist_enable" = "1" - - # Disable DPTF - register "dptf_enable" = "0" - - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - - # Send an extra VR mailbox command for the PS4 exit issue - # register "SendVrMbxCmd" = "2" - -# Graphics (soc/intel/skylake/graphics.c) - register "panel_cfg" = "{ - .up_delay_ms= 200,// T3 - .down_delay_ms= 0,// T10 - .cycle_delay_ms = 500,// T12 - .backlight_on_delay_ms=50,// T7 - .backlight_off_delay_ms = 0,// T9 - .backlight_pwm_hz = 200, - }" - - # IGD Displays - register "gfx" = "GMA_STATIC_DISPLAYS(0)" - -# CPU (soc/intel/skylake/chip.c) - # Power limit - register "power_limits_config" = "{ - .tdp_pl1_override = 20, - .tdp_pl2_override = 30, - }" - - # FSP configuration - register "SaGv" = "SaGv_Enabled" - - # Serial I/O - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0]= PchSerialIoPci, - [PchSerialIoIndexI2C1]= PchSerialIoPci, - [PchSerialIoIndexI2C2]= PchSerialIoPci, - [PchSerialIoIndexI2C3]= PchSerialIoPci, - [PchSerialIoIndexI2C4]= PchSerialIoDisabled, - [PchSerialIoIndexI2C5]= PchSerialIoPci, - [PchSerialIoIndexSpi0]= PchSerialIoPci, - [PchSerialIoIndexSpi1]= PchSerialIoPci, - [PchSerialIoIndexUart0] = PchSerialIoSkipInit, - [PchSerialIoIndexUart1] = PchSerialIoDisabled, - [PchSerialIoIndexUart2] = PchSerialIoSkipInit, - }" - - # Power - register "PmConfigSlpS3MinAssert" = "3" # 50ms - register "PmConfigSlpS4MinAssert" = "3" # 1s - register "PmConfigSlpSusMinAssert" = "3" # 500ms - register "PmConfigSlpAMinAssert" = "3" # 2s - - # Thermal - register "tcc_offset" = "5" - -# PM Util (soc/intel/skylake/pmutil.c) - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) - register "gpe0_dw0" = "GPP_B" - register "gpe0_dw1" = "GPP_C" - register "gpe0_dw2" = "GPP_E" - - # Enable the correct decode ranges on the LPC bus. - register "lpc_ioe" = "LPC_IOE_EC_4E_4F | LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66" - -# Actual device tree. - device cpu_cluster 0 on - device lapic 0 on end - end - - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal Device - device pci 14.0 on # USB xHCI - # USB2 - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A port 2 - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # uSD Card - register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A port 3 - register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Camera - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Actual Bluetooth port - - # USB3 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" - end - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on # I2C #0 - chip drivers/i2c/hid - register "generic.hid" = ""StarPoint"" - register "generic.desc" = ""Touchpad"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" - register "generic.probed" = "1" - register "hid_desc_reg_offset" = "0x20" - device i2c 2c on end - end - end - device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 on # SATA - register "SataSalpSupport" = "0" - register "SataMode" = "0" - - # Port 1 - register "SataPortsEnable[1]" = "1" - register "SataPortsDevSlp[1]" = "0" - - # Port 2 - register "SataPortsEnable[2]" = "1" - register "SataPortsDevSlp[2]" = "0" - end - device pci 19.0 on end # UART #2 - device pci 19.1 off end # I2C #4 - device pci 19.2 off end # I2C #5 - device pci 1c.0 off end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 on # PCI Express Port 6 (WLAN) - register "PcieRpEnable[5]" = "1" - register "PcieRpClkReqSupport[5]" = "1" - register "PcieRpClkReqNumber[5]" = "4" - register "PcieRpClkSrcNumber[5]" = "4" - register "PcieRpLtrEnable[5]" = "1" - chip drivers/wifi/generic - device pci 00.0 on end - end - end - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on # PCI Express Port 9(SSD x4) - device pci 00.0 on end - register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - register "PcieRpClkReqNumber[8]" = "0" - register "PcieRpClkSrcNumber[8]" = "0" - register "PcieRpLtrEnable[8]" = "1" - smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" - end - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1e.4 off end # eMMC - device pci 1e.5 off end # SDIO - device pci 1e.6 off end # SDCard - device pci 1f.0 on # LPC Interface - # LPC configuration from lspci -s 1f.0 -xxx - # Address 0x84: Decode 0x680 - 0x68F - register "gen1_dec" = "0x000c0681" - # Address 0x88: Decode - register "gen2_dec" = "0x000c1641" - # Address 0x8C: Decode 0x200 - 0x2FF - register "gen3_dec" = "0x00000069" - # Address 0x90: Decode 0x80 - 0x8F (Port 80) - register "gen4_dec" = "0x0000006d" - register "serirq_mode" = "SERIRQ_CONTINUOUS" - - chip ec/starlabs/it8987 - # Port 4Eh/4Fh - device pnp 4e.0 on # IO Interface - end - end - end - device pci 1f.1 off end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - subsystemid 0x10ec 0x111e - device pci 1f.4 on end # SMBus - device pci 1f.5 off end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads b/src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads deleted file mode 100644 index 8402b39a94..0000000000 --- a/src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads +++ /dev/null @@ -1,18 +0,0 @@ --- SPDX-License-Identifier: GPL-2.0-or-later - -with HW.GFX.GMA; -with HW.GFX.GMA.Display_Probing; - -use HW.GFX.GMA; -use HW.GFX.GMA.Display_Probing; - -private package GMA.Mainboard is - - ports : constant Port_List := - (DP1, -- USB-C - HDMI1, -- USB-C - HDMI2, -- HDMI - eDP, - others => Disabled); - -end GMA.Mainboard; diff --git a/src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h b/src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h deleted file mode 100644 index 803007d0f0..0000000000 --- a/src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h +++ /dev/null @@ -1,203 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _VARIANT_GPIO_H_ -#define _VARIANT_GPIO_H_ - -#include "baseboard/variants.h" - -#ifndef __ACPI__ - -/* - * All definitions are taken from a comparison of the output of "inteltool -a" - * using the stock BIOS and with coreboot. - */ - -/* Early pad configuration in romstage. */ -static const struct pad_config early_gpio_table[] = { - -}; - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - -/* Pad configuration in ramstage. */ -static const struct pad_config gpio_table[] = { - PAD_CFG_NF(GPD0, NONE, PWROK, NF1), - PAD_CFG_NF(GPD1, NONE, PWROK, NF1), - _PAD_CFG_STRUCT(GPD2, 0x04000300, 0x1000), - PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), - PAD_CFG_NF(GPD4, NONE, PWROK, NF1), - PAD_CFG_NF(GPD5, NONE, PWROK, NF1), - PAD_CFG_NF(GPD6, NONE, PWROK, NF1), - _PAD_CFG_STRUCT(GPD7, 0x04000101, 0x1000), - PAD_CFG_NF(GPD8, NONE, PWROK, NF1), - PAD_CFG_GPI(GPD9, DN_20K, PWROK), - PAD_CFG_NF(GPD10, DN_20K, PWROK, NF1), - PAD_CFG_NF(GPD11, DN_20K, PWROK, NF1), - PAD_NC(GPP_A0, NONE), - PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), - PAD_NC(GPP_A7, NONE), - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), - PAD_NC(GPP_A10, DN_20K), - PAD_CFG_GPI(GPP_A11, DN_20K, DEEP), - PAD_NC(GPP_A12, NONE), - PAD_NC(GPP_A13, DN_20K), - PAD_NC(GPP_A14, DN_20K), - PAD_NC(GPP_A15, DN_20K), - PAD_NC(GPP_A16, DN_20K), - PAD_NC(GPP_A17, DN_20K), - PAD_NC(GPP_A18, DN_20K), - PAD_NC(GPP_A19, DN_20K), - PAD_NC(GPP_A20, DN_20K), - PAD_NC(GPP_A21, DN_20K), - PAD_NC(GPP_A22, DN_20K), - PAD_NC(GPP_A23, DN_20K), - PAD_NC(GPP_B0, DN_20K), - PAD_NC(GPP_B1, DN_20K), - PAD_NC(GPP_B2, DN_20K), - PAD_NC(GPP_B3, DN_20K), - PAD_CFG_TERM_GPO(GPP_B4, 1, UP_20K, DEEP), - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), - PAD_CFG_GPI(GPP_B6, DN_20K, DEEP), - PAD_CFG_NF(GPP_B7, DN_20K, DEEP, NF1), - PAD_CFG_NF(GPP_B8, DN_20K, DEEP, NF1), - PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_B10, DN_20K, DEEP, NF1), - PAD_NC(GPP_B11, DN_20K), - PAD_NC(GPP_B12, DN_20K), - PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - PAD_NC(GPP_B14, DN_20K), - PAD_NC(GPP_B15, DN_20K), - PAD_NC(GPP_B16, DN_20K), - PAD_NC(GPP_B17, DN_20K), - PAD_NC(GPP_B18, DN_20K), - PAD_NC(GPP_B19, DN_20K), - PAD_NC(GPP_B20, DN_20K), - PAD_NC(GPP_B21, DN_20K), - PAD_NC(GPP_B22, DN_20K), - PAD_NC(GPP_B23, DN_20K), - PAD_CFG_NF(GPP_C0, UP_20K, DEEP, NF1), - PAD_CFG_NF(GPP_C1, UP_20K, DEEP, NF1), - PAD_NC(GPP_C2, DN_20K), - PAD_NC(GPP_C3, DN_20K), - PAD_NC(GPP_C4, DN_20K), - PAD_NC(GPP_C5, DN_20K), - PAD_NC(GPP_C6, DN_20K), - PAD_NC(GPP_C7, DN_20K), - PAD_CFG_NF(GPP_C8, UP_20K, DEEP, NF1), - PAD_CFG_NF(GPP_C9, UP_20K, DEEP, NF1), - _PAD_CFG_STRUCT(GPP_C10, 0x44000301, 0x3000), - PAD_CFG_NF(GPP_C11, UP_20K, DEEP, NF1), - PAD_NC(GPP_C12, UP_20K), - PAD_NC(GPP_C13, UP_20K), - PAD_NC(GPP_C14, UP_20K), - PAD_NC(GPP_C15, UP_20K), - PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), - PAD_NC(GPP_C22, NONE), - _PAD_CFG_STRUCT(GPP_C23, 0x80100100, 0x3000), - PAD_NC(GPP_D0, DN_20K), - PAD_NC(GPP_D1, DN_20K), - PAD_NC(GPP_D2, DN_20K), - PAD_NC(GPP_D3, DN_20K), - PAD_NC(GPP_D4, DN_20K), - PAD_NC(GPP_D5, DN_20K), - PAD_NC(GPP_D6, DN_20K), - PAD_NC(GPP_D7, DN_20K), - PAD_NC(GPP_D8, DN_20K), - PAD_NC(GPP_D9, DN_20K), - PAD_NC(GPP_D10, DN_20K), - PAD_NC(GPP_D11, DN_20K), - PAD_NC(GPP_D12, DN_20K), - PAD_NC(GPP_D13, DN_20K), - PAD_NC(GPP_D14, DN_20K), - PAD_NC(GPP_D15, DN_20K), - PAD_NC(GPP_D16, DN_20K), - PAD_NC(GPP_D17, DN_20K), - PAD_NC(GPP_D18, DN_20K), - PAD_NC(GPP_D19, DN_20K), - PAD_CFG_TERM_GPO(GPP_D20, 1, UP_20K, DEEP), - PAD_NC(GPP_D21, DN_20K), - PAD_NC(GPP_D22, DN_20K), - PAD_NC(GPP_D23, DN_20K), - PAD_NC(GPP_E0, DN_20K), - PAD_NC(GPP_E1, DN_20K), - _PAD_CFG_STRUCT(GPP_E2, 0x44000601, 0x0000), - PAD_NC(GPP_E3, DN_20K), - PAD_NC(GPP_E4, DN_20K), - PAD_NC(GPP_E5, DN_20K), - PAD_CFG_NF(GPP_E6, NONE, PWROK, NF1), - PAD_NC(GPP_E7, DN_20K), - PAD_NC(GPP_E8, DN_20K), - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), - PAD_NC(GPP_E12, DN_20K), - PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), - _PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0000), - _PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000), - PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), - PAD_NC(GPP_E20, DN_20K), - PAD_NC(GPP_E21, DN_20K), - PAD_NC(GPP_E22, DN_20K), - PAD_NC(GPP_E23, DN_20K), - PAD_NC(GPP_F0, DN_20K), - PAD_NC(GPP_F1, DN_20K), - PAD_NC(GPP_F2, DN_20K), - PAD_NC(GPP_F3, DN_20K), - PAD_NC(GPP_F4, DN_20K), - PAD_NC(GPP_F5, DN_20K), - PAD_NC(GPP_F6, DN_20K), - PAD_NC(GPP_F7, DN_20K), - PAD_CFG_NF(GPP_F8, DN_20K, DEEP, NF1), - PAD_CFG_NF(GPP_F9, DN_20K, DEEP, NF1), - PAD_NC(GPP_F10, DN_20K), - PAD_NC(GPP_F11, DN_20K), - PAD_NC(GPP_F12, DN_20K), - PAD_NC(GPP_F13, DN_20K), - PAD_NC(GPP_F14, DN_20K), - PAD_NC(GPP_F15, DN_20K), - PAD_NC(GPP_F16, DN_20K), - PAD_NC(GPP_F17, DN_20K), - PAD_NC(GPP_F18, DN_20K), - PAD_NC(GPP_F19, DN_20K), - PAD_NC(GPP_F20, DN_20K), - PAD_NC(GPP_F21, DN_20K), - PAD_NC(GPP_F22, DN_20K), - PAD_NC(GPP_F23, DN_20K), - PAD_CFG_GPI(GPP_G0, DN_20K, DEEP), - PAD_CFG_GPI(GPP_G1, DN_20K, DEEP), - PAD_CFG_GPI(GPP_G2, DN_20K, DEEP), - PAD_CFG_GPI(GPP_G3, DN_20K, DEEP), - PAD_CFG_GPI(GPP_G4, DN_20K, DEEP), - PAD_CFG_GPI(GPP_G5, DN_20K, DEEP), - PAD_CFG_GPI(GPP_G6, DN_20K, DEEP), - PAD_CFG_GPI(GPP_G7, DN_20K, DEEP), - -}; - -const struct pad_config *variant_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -#endif - -#endif diff --git a/src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h b/src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h deleted file mode 100644 index 2ad909624c..0000000000 --- a/src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _HDA_VERB_H_ -#define _HDA_VERB_H_ - -#include <device/azalia_device.h> -#include <device/azalia.h> - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269 - 0xffffffff, // Subsystem ID - 0x0000002b, // Number of jacks (NID entries) - /* Rest Codec First */ - AZALIA_RESET(0x1), - /* HDA Codec Subsystem ID Verb-table - HDA Codec Subsystem ID : 0x10EC111E */ - 0x0017201E, - 0x00172111, - 0x001722EC, - 0x00172310, - /* Pin Widget Verb-table */ - AZALIA_PIN_CFG(0, 0x01, 0x00000000), - AZALIA_PIN_CFG(0, 0x12, 0x90a61120), - AZALIA_PIN_CFG(0, 0x14, 0x90171110), - AZALIA_PIN_CFG(0, 0x15, 0x042B1010), - AZALIA_PIN_CFG(0, 0x17, 0x411111F0), - AZALIA_PIN_CFG(0, 0x18, 0x04AB1020), - AZALIA_PIN_CFG(0, 0x19, 0x411111F0), - AZALIA_PIN_CFG(0, 0x1A, 0x411111F0), - AZALIA_PIN_CFG(0, 0x1B, 0x411111F0), - AZALIA_PIN_CFG(0, 0x1D, 0x411111F0), - AZALIA_PIN_CFG(0, 0x1E, 0x411111F0), - /* Widget node 0x20 */ - 0x02050018, - 0x02040184, /* Stock: 0x02043984 */ - 0x0205001C, - 0x02040800, - /* Widget node 0x20 - 1 */ - 0x02050024, - 0x02040000, - 0x02050004, - 0x02040080, - /* Widget node 0x20 - 2 */ - 0x02050008, - 0x02040300, - 0x0205000C, - 0x02043F00, - /* Widget node 0x20 - 3 */ - 0x02050015, - 0x02048002, - 0x02050015, - 0x02048002, - /* Widget node 0x0C */ - 0x00C37080, - 0x00270610, - 0x00D37080, - 0x00370610, - - 0x8086280b, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ - - AZALIA_SUBVENDOR(2, 0x80860101), - - AZALIA_PIN_CFG(2, 0x05, 0x18560010), - AZALIA_PIN_CFG(2, 0x06, 0x18560010), - AZALIA_PIN_CFG(2, 0x07, 0x18560010), - -}; - -const u32 pc_beep_verbs[] = { -}; - -AZALIA_ARRAY_SIZES; - -#endif diff --git a/src/mainboard/starlabs/labtop/variants/kbl/romstage.c b/src/mainboard/starlabs/labtop/variants/kbl/romstage.c deleted file mode 100644 index 4f1b7e05d5..0000000000 --- a/src/mainboard/starlabs/labtop/variants/kbl/romstage.c +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <assert.h> -#include <console/console.h> -#include <soc/romstage.h> -#include <spd_bin.h> -#include "spd/spd_util.c" -#include "spd/spd.h" -#include <ec/acpi/ec.h> -#include <stdint.h> - -void mainboard_memory_init_params(FSPM_UPD *mupd) -{ - FSP_M_CONFIG *mem_cfg; - mem_cfg = &mupd->FspmConfig; - - /* Use the correct entry in the SPD table defined in Makefile.inc */ - u8 spd_index = 6; - printk(BIOS_INFO, "SPD index %d\n", spd_index); - - mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); - mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); - mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); - mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); - - mem_cfg->DqPinsInterleaved = 0; - mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; - /* Memory leak is ok since we have memory mapped boot media */ - // TODO evaluate google/eve way of loading - mem_cfg->MemorySpdPtr00 = spd_cbfs_map(spd_index); - if (!mem_cfg->MemorySpdPtr00) - die("spd.bin not found\n"); - mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; - - mupd->FspmTestConfig.DmiVc1 = 1; -} |