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-rw-r--r--src/mainboard/sapphire/pureplatinumh61/devicetree.cb17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
index 87d1532df9..c44e2f3772 100644
--- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
+++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
@@ -9,6 +9,23 @@ chip northbridge/intel/sandybridge
register "pcie_port_coalesce" = "true"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x33"
+ register "usb_port_config" = "{
+ { 1, 0, 0 },
+ { 1, 0, 0 },
+ { 1, 0, 1 },
+ { 1, 0, 1 },
+ { 1, 0, 2 },
+ { 1, 0, 2 },
+ { 1, 0, 3 },
+ { 1, 0, 3 },
+ { 1, 0, 4 },
+ { 1, 0, 4 },
+ { 1, 0, 6 },
+ { 1, 0, 5 },
+ { 1, 0, 5 },
+ { 1, 0, 6 }
+ }"
+
register "spi.opprefixes" = "{ 0x50, 0x06 }"
register "spi.ops" = "{{0x01, WRITE_NO_ADDR},
{0x02, WRITE_WITH_ADDR},