diff options
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree_m.cb | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 95b006e2f6..a6bad136b6 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -83,7 +83,7 @@ chip soc/intel/alderlake }" # Hybrid storage mode - register "hybrid_storage_mode" = "1" + register "hybrid_storage_mode" = "true" # Enable CPU PCIE RP 1 using CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 0b3a3efea0..922b673ce2 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -76,7 +76,7 @@ chip soc/intel/alderlake }" # Hybrid storage mode - register "hybrid_storage_mode" = "1" + register "hybrid_storage_mode" = "true" # Enable CPU PCIE RP 1 using CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ |