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-rw-r--r--src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
index 346b98eef2..a36c849779 100644
--- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
@@ -17,9 +17,6 @@ chip soc/intel/alderlake
# DPTF enable
register "dptf_enable" = "1"
- # Enable heci communication
- register "HeciEnabled" = "1"
-
# Enable CNVi BT
register "CnviBtCore" = "true"