diff options
Diffstat (limited to 'src/mainboard')
7 files changed, 0 insertions, 21 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 346b98eef2..a36c849779 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -17,9 +17,6 @@ chip soc/intel/alderlake # DPTF enable register "dptf_enable" = "1" - # Enable heci communication - register "HeciEnabled" = "1" - # Enable CNVi BT register "CnviBtCore" = "true" diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 7323b106c7..ee0fbce406 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -19,9 +19,6 @@ chip soc/intel/alderlake register "tcc_offset" = "10" # TCC of 90 - # Enable heci communication - register "HeciEnabled" = "1" - # Enable CNVi BT register "CnviBtCore" = "true" diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 8f60e42970..9bd99b18f7 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -8,9 +8,6 @@ chip soc/intel/alderlake register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E" - # Enable HECI1 interface - register "HeciEnabled" = "1" - # FSP configuration # Enable CNVi BT diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index ab9983095b..c637ec3d54 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -18,9 +18,6 @@ chip soc/intel/alderlake register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E" - # Enable HECI1 communication - register "HeciEnabled" = "1" - # FSP configuration register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-C port 0 register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-C port 1 diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index cec0422849..f013596b06 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -8,9 +8,6 @@ chip soc/intel/alderlake register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E" - # Enable HECI1 interface - register "HeciEnabled" = "1" - # FSP configuration # Enable CNVi BT diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 575739241e..63d3da423b 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -16,9 +16,6 @@ chip soc/intel/alderlake register "TcssAuxOri" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A5, .pad_auxn_dc = GPP_A6}" - # Enable heci communication - register "HeciEnabled" = "1" - # Enable CNVi Bluetooth register "CnviBtCore" = "true" diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb index 513e3b83bf..cf2e27041e 100644 --- a/src/mainboard/prodrive/atlas/devicetree.cb +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -8,9 +8,6 @@ chip soc/intel/alderlake register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E" - # Enable HECI1 interface - register "HeciEnabled" = "1" - device domain 0 on device ref pcie5 on end device ref igpu on end |