diff options
Diffstat (limited to 'src/mainboard/bitworks/ims')
| -rw-r--r-- | src/mainboard/bitworks/ims/Config.lb | 136 | ||||
| -rw-r--r-- | src/mainboard/bitworks/ims/Options.lb | 157 | ||||
| -rw-r--r-- | src/mainboard/bitworks/ims/auto.c | 96 | ||||
| -rw-r--r-- | src/mainboard/bitworks/ims/chip.h | 5 | ||||
| -rw-r--r-- | src/mainboard/bitworks/ims/cmos.layout | 74 | ||||
| -rw-r--r-- | src/mainboard/bitworks/ims/debug.c | 66 | ||||
| -rw-r--r-- | src/mainboard/bitworks/ims/failover.c | 32 | ||||
| -rw-r--r-- | src/mainboard/bitworks/ims/mainboard.c | 7 | ||||
| -rw-r--r-- | src/mainboard/bitworks/ims/reset.c | 43 |
9 files changed, 0 insertions, 616 deletions
diff --git a/src/mainboard/bitworks/ims/Config.lb b/src/mainboard/bitworks/ims/Config.lb deleted file mode 100644 index 69b08279a2..0000000000 --- a/src/mainboard/bitworks/ims/Config.lb +++ /dev/null @@ -1,136 +0,0 @@ -## -## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end - -## -## Compute the start location and size size of -## The linuxBIOS bootloader. -## -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) - -## -## Compute where this copy of linuxBIOS will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up linuxBIOS, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -#if HAVE_PIRQ_TABLE object irq_tables.o end -#object reset.o - -## -## Romcc output -## -makerule ./failover.E - depends "$(MAINBOARD)/failover.c ./romcc" - action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ./romcc" - action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" -end - -makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ./romcc" - action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ./romcc" - action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit linuxBIOS entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where linuxBIOS is entered) -## -if USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of linuxBIOS startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu/enable_fpu.inc -mainboardinit cpu/x86/mmx/enable_mmx.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx/disable_mmx.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/intel/i440bx - device pci_domain 0 on - end - - chip cpu/intel/socket_PGA370 - end - -end - diff --git a/src/mainboard/bitworks/ims/Options.lb b/src/mainboard/bitworks/ims/Options.lb deleted file mode 100644 index 0c13bf6683..0000000000 --- a/src/mainboard/bitworks/ims/Options.lb +++ /dev/null @@ -1,157 +0,0 @@ -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE -uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses CONFIG_UDELAY_TSC - -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 512*1024 - -### -### Build options -### - -## -## Build code for the fallback boot -## -default HAVE_FALLBACK_BOOT=1 - -## -## no MP table -## -default HAVE_MP_TABLE=0 - -## -## Build code to reset the motherboard from linuxBIOS -## -default HAVE_HARD_RESET=0 - -## -## Build code to export a programmable irq routing table -## -default HAVE_PIRQ_TABLE=0 -default IRQ_SLOT_COUNT=4 -#object irq_tables.o - -## -## Build code to export a CMOS option table -## -default HAVE_OPTION_TABLE=0 - -### -### LinuxBIOS layout values -### - -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 - -## -## Use a small 8K stack -## -default STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 - -default _RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 - -# Select the serial console base port -default TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 - -## -### Select the linuxBIOS loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=9 -## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=9 - -default CONFIG_UDELAY_TSC=1 - -end - diff --git a/src/mainboard/bitworks/ims/auto.c b/src/mainboard/bitworks/ims/auto.c deleted file mode 100644 index bfd10afec2..0000000000 --- a/src/mainboard/bitworks/ims/auto.c +++ /dev/null @@ -1,96 +0,0 @@ -#define ASSEMBLY 1 - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <arch/romcc_io.h> -#include <arch/hlt.h> -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" -#include "ram/ramtest.c" -#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" -#include "superio/nsc/pc87351/pc87351_early_serial.c" -#include "northbridge/intel/i440bx/raminit.h" -#include "cpu/x86/mtrr/earlymtrr.c" -#include "cpu/x86/bist.h" - -#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1) - -void udelay(int usecs) -{ - int i; - for(i = 0; i < usecs; i++) - outb(i&0xff, 0x80); -} - -#include "debug.c" -#include "lib/delay.c" - -static void enable_shadow_ram(void) -{ - uint8_t shadowreg; - /* dev 0 for northbridge */ - shadowreg = pci_read_config8(0, 0x59); - /* 0xf0000-0xfffff */ - shadowreg |= 0x30; - pci_write_config8(0, 0x59, shadowreg); -} - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i440bx/raminit.c" -#include "northbridge/intel/i440bx/debug.c" -#include "sdram/generic_sdram.c" - -static void main(unsigned long bist) -{ - static const struct mem_controller memctrl[] = { - { - .d0 = PCI_DEV(0, 0, 0), - .channel0 = { - (0xa << 3) | 0, - (0xa << 3) | 1, - (0xa << 3) | 2, - (0xa << 3) | 3, - }, - } - }; - - if (bist == 0) { - early_mtrr_init(); - } - pc87351_enable_serial(SERIAL_DEV, TTYS0_BASE); - uart_init(); - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - enable_shadow_ram(); - - enable_smbus(); - - dump_spd_registers(&memctrl[0]); - - sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); - - /* Check whether RAM is working. - * - * Do _not_ check the area from 640 KB - 1 MB, as that's not really - * RAM, but rather reserved for various other things: - * - * - 640 KB - 768 KB: Video Buffer Area - * - 768 KB - 896 KB: Expansion Area - * - 896 KB - 960 KB: Extended System BIOS Area - * - 960 KB - 1 MB: Memory (BIOS Area) - System BIOS Area - * - * Trying to check these areas will fail. - */ - /* TODO: This is currently hardcoded to check 64 MB. */ - ram_check(0x00000000, 0x0009ffff); /* 0 - 640 KB */ - ram_check(0x00100000, 0x007c0000); /* 1 MB - 64 MB */ -} diff --git a/src/mainboard/bitworks/ims/chip.h b/src/mainboard/bitworks/ims/chip.h deleted file mode 100644 index d0fe923429..0000000000 --- a/src/mainboard/bitworks/ims/chip.h +++ /dev/null @@ -1,5 +0,0 @@ -extern struct chip_operations mainboard_bitworks_ims_ops; - -struct mainboard_bitworks_ims_config { - int nothing; -}; diff --git a/src/mainboard/bitworks/ims/cmos.layout b/src/mainboard/bitworks/ims/cmos.layout deleted file mode 100644 index 5ba4c032c1..0000000000 --- a/src/mainboard/bitworks/ims/cmos.layout +++ /dev/null @@ -1,74 +0,0 @@ -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD -7 10 Fallback_Floppy -#7 3 ROM - -checksums - -checksum 392 1007 1008 - - diff --git a/src/mainboard/bitworks/ims/debug.c b/src/mainboard/bitworks/ims/debug.c deleted file mode 100644 index 7eeabdef47..0000000000 --- a/src/mainboard/bitworks/ims/debug.c +++ /dev/null @@ -1,66 +0,0 @@ - -static void print_debug_pci_dev(unsigned dev) -{ - print_debug("PCI: "); - print_debug_hex8((dev >> 16) & 0xff); - print_debug_char(':'); - print_debug_hex8((dev >> 11) & 0x1f); - print_debug_char('.'); - print_debug_hex8((dev >> 8) & 7); -} - -static void print_pci_devices(void) -{ - device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - print_debug_pci_dev(dev); - print_debug("\r\n"); - } -} - -static void dump_pci_device(unsigned dev) -{ - int i; - print_debug_pci_dev(dev); - print_debug("\r\n"); - - for(i = 0; i <= 255; i++) { - unsigned char val; - if ((i & 0x0f) == 0) { - print_debug_hex8(i); - print_debug_char(':'); - } - val = pci_read_config8(dev, i); - print_debug_char(' '); - print_debug_hex8(val); - if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); - } - } -} - -static void dump_pci_devices(void) -{ - device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } -} diff --git a/src/mainboard/bitworks/ims/failover.c b/src/mainboard/bitworks/ims/failover.c deleted file mode 100644 index bdcb9eaed2..0000000000 --- a/src/mainboard/bitworks/ims/failover.c +++ /dev/null @@ -1,32 +0,0 @@ -#define ASSEMBLY 1 -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include "arch/romcc_io.h" -#include "pc80/mc146818rtc_early.c" - -static unsigned long main(unsigned long bist) -{ - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: - return bist; -} diff --git a/src/mainboard/bitworks/ims/mainboard.c b/src/mainboard/bitworks/ims/mainboard.c deleted file mode 100644 index 8da5632823..0000000000 --- a/src/mainboard/bitworks/ims/mainboard.c +++ /dev/null @@ -1,7 +0,0 @@ -#include <device/device.h> -#include "chip.h" - -struct chip_operations mainboard_bitworks_ims_ops = { - CHIP_NAME("Bitworks IMS Mainboard") -}; - diff --git a/src/mainboard/bitworks/ims/reset.c b/src/mainboard/bitworks/ims/reset.c deleted file mode 100644 index 5796e17dc8..0000000000 --- a/src/mainboard/bitworks/ims/reset.c +++ /dev/null @@ -1,43 +0,0 @@ -#if 0 -//#include "arch/romcc_io.h" -#include <arch/io.h> - -typedef unsigned device_t; - -#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFF) << 16) | \ - (((DEV) & 0x1f) << 11) | \ - (((FN) & 0x7) << 8)) - -static void pci_write_config8(device_t dev, unsigned where, unsigned char value) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outb(value, 0xCFC + (addr & 3)); -} - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -static unsigned pci_read_config32(device_t dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - -#include "../../../northbridge/amd/amdk8/reset_test.c" - -void hard_reset(void) -{ - set_bios_reset(); - pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1); -} -#endif |