diff options
Diffstat (limited to 'src/drivers/intel/fsp2_0')
| -rw-r--r-- | src/drivers/intel/fsp2_0/Kconfig | 8 | ||||
| -rw-r--r-- | src/drivers/intel/fsp2_0/save_mrc_data.c | 4 |
2 files changed, 12 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 8c360630b8..21327379ae 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -381,4 +381,12 @@ config FSP_ENABLE_SERIAL_DEBUG coreboot native debug driver when coreboot has integrated the debug FSP binaries. coreboot disables serial messages when this config is not enabled. +config SAVE_MRC_AFTER_FSPS + bool + default n + depends on XEON_SP_COMMON_BASE + help + Save MRC training data after FSP-S. Select this on platforms that generate MRC + cache HOB data as part of FSP-S rather than FSP-M. + endif diff --git a/src/drivers/intel/fsp2_0/save_mrc_data.c b/src/drivers/intel/fsp2_0/save_mrc_data.c index 7313967da3..8742c24bc5 100644 --- a/src/drivers/intel/fsp2_0/save_mrc_data.c +++ b/src/drivers/intel/fsp2_0/save_mrc_data.c @@ -43,4 +43,8 @@ static void save_mrc_data(void *unused) * Should be done before ramstage_cse_fw_sync() to avoid traning memory twice on * a cold boot after a full firmware update. */ +#if !CONFIG(SAVE_MRC_AFTER_FSPS) BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, save_mrc_data, NULL); +#elif CONFIG(SAVE_MRC_AFTER_FSPS) +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, save_mrc_data, NULL); +#endif |