diff options
Diffstat (limited to 'src/cpu/intel/fsp_model_406dx/Makefile.inc')
| -rw-r--r-- | src/cpu/intel/fsp_model_406dx/Makefile.inc | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc new file mode 100644 index 0000000000..f28e531098 --- /dev/null +++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc @@ -0,0 +1,28 @@ +# +# This file is part of the coreboot project. +# +# Copyrignt (C) 2014 Sage Electronic Engineering, LLC. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. +# + +ramstage-y += model_406dx_init.c +subdirs-y += ../../x86/name + +ramstage-y += acpi.c + +CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx +# We don't have microcode for this CPU +# Use CONFIG_CPU_MICROCODE_CBFS_EXTERNAL with a binary microcode file +# cpu_microcode_bins += ??? |