diff options
28 files changed, 0 insertions, 336 deletions
diff --git a/src/mainboard/amd/db800/Config.lb b/src/mainboard/amd/db800/Config.lb index 5b35a06f1a..e4edd27e3e 100644 --- a/src/mainboard/amd/db800/Config.lb +++ b/src/mainboard/amd/db800/Config.lb @@ -50,7 +50,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end -if USE_DCACHE_RAM #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -58,8 +57,6 @@ if USE_DCACHE_RAM action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end - ## ## Build our 16 bit and 32 bit coreboot entry code @@ -108,10 +105,8 @@ end ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary Configuration files diff --git a/src/mainboard/amd/dbm690t/Config.lb b/src/mainboard/amd/dbm690t/Config.lb index fdff4bd6c9..24316ba6c1 100644 --- a/src/mainboard/amd/dbm690t/Config.lb +++ b/src/mainboard/amd/dbm690t/Config.lb @@ -83,8 +83,6 @@ end #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -103,14 +101,12 @@ if USE_DCACHE_RAM end -end ## ## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -118,7 +114,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -137,12 +132,10 @@ end mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -150,12 +143,7 @@ end ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM - ldscript /arch/i386/lib/failover.lds - else ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc - end end ### @@ -165,16 +153,12 @@ end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## diff --git a/src/mainboard/amd/norwich/Config.lb b/src/mainboard/amd/norwich/Config.lb index b42a98bd6f..3a6fd23edf 100644 --- a/src/mainboard/amd/norwich/Config.lb +++ b/src/mainboard/amd/norwich/Config.lb @@ -52,7 +52,6 @@ end #object reset.o -if USE_DCACHE_RAM #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -60,8 +59,6 @@ if USE_DCACHE_RAM action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end - ## ## Build our 16 bit and 32 bit coreboot entry code @@ -110,10 +107,8 @@ end ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary Configuration files diff --git a/src/mainboard/amd/pistachio/Config.lb b/src/mainboard/amd/pistachio/Config.lb index 186a60970e..c1f513609e 100644 --- a/src/mainboard/amd/pistachio/Config.lb +++ b/src/mainboard/amd/pistachio/Config.lb @@ -83,8 +83,6 @@ end #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -103,14 +101,12 @@ if USE_DCACHE_RAM end -end ## ## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -118,7 +114,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -137,12 +132,10 @@ end mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -150,12 +143,7 @@ end ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM - ldscript /arch/i386/lib/failover.lds - else ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc - end end ### @@ -165,16 +153,12 @@ end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## diff --git a/src/mainboard/amd/serengeti_cheetah/Config.lb b/src/mainboard/amd/serengeti_cheetah/Config.lb index 039bf4bb05..a0ff3aef73 100644 --- a/src/mainboard/amd/serengeti_cheetah/Config.lb +++ b/src/mainboard/amd/serengeti_cheetah/Config.lb @@ -122,8 +122,6 @@ if HAVE_ACPI_TABLES end end -if USE_DCACHE_RAM - if CONFIG_USE_INIT # compile cache_as_ram.c to auto.o makerule ./cache_as_ram_auto.o @@ -140,7 +138,6 @@ if USE_DCACHE_RAM action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end if USE_FAILOVER_IMAGE else @@ -170,7 +167,6 @@ else end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -178,7 +174,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -207,12 +202,10 @@ end mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -221,15 +214,11 @@ end ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end @@ -240,16 +229,12 @@ end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb index 3689ba2abc..d01785a1cf 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb @@ -129,7 +129,6 @@ if HAVE_ACPI_TABLES end end -if USE_DCACHE_RAM makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c if CONFIG_USE_INIT @@ -149,7 +148,6 @@ if USE_DCACHE_RAM end end -end if USE_FAILOVER_IMAGE else @@ -179,7 +177,6 @@ else end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -187,7 +184,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -217,12 +213,10 @@ end mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -231,15 +225,11 @@ end ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end @@ -250,16 +240,12 @@ end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## diff --git a/src/mainboard/artecgroup/dbe61/Config.lb b/src/mainboard/artecgroup/dbe61/Config.lb index 6184d83a25..a39cbdfe8c 100644 --- a/src/mainboard/artecgroup/dbe61/Config.lb +++ b/src/mainboard/artecgroup/dbe61/Config.lb @@ -47,8 +47,6 @@ driver mainboard.o if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o - -if USE_DCACHE_RAM #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -56,8 +54,6 @@ if USE_DCACHE_RAM action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end - ## ## Build our 16 bit and 32 bit coreboot entry code @@ -106,10 +102,8 @@ end ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary Configuration files diff --git a/src/mainboard/asus/a8n_e/Config.lb b/src/mainboard/asus/a8n_e/Config.lb index 410971c89e..a082ca957d 100644 --- a/src/mainboard/asus/a8n_e/Config.lb +++ b/src/mainboard/asus/a8n_e/Config.lb @@ -54,7 +54,6 @@ driver mainboard.o object get_bus_conf.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -68,7 +67,6 @@ if USE_DCACHE_RAM action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -81,12 +79,10 @@ else end end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds ldscript /cpu/amd/car/cache_as_ram.lds end -end if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -104,10 +100,6 @@ else ldscript /cpu/x86/32bit/reset32.lds end end -if USE_DCACHE_RAM -else - mainboardinit arch/i386/lib/cpu_reset.inc -end # Include an ID string (for safe flashing). mainboardinit southbridge/nvidia/ck804/id.inc ldscript /southbridge/nvidia/ck804/id.lds @@ -123,29 +115,21 @@ else ldscript /southbridge/nvidia/ck804/romstrap.lds end end -if USE_DCACHE_RAM mainboardinit cpu/amd/car/cache_as_ram.inc -end if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end -if USE_DCACHE_RAM if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -end config chip.h chip northbridge/amd/amdk8/root_complex # Root complex diff --git a/src/mainboard/asus/a8v-e_se/Config.lb b/src/mainboard/asus/a8v-e_se/Config.lb index 08be016ea0..9c094de560 100644 --- a/src/mainboard/asus/a8v-e_se/Config.lb +++ b/src/mainboard/asus/a8v-e_se/Config.lb @@ -52,7 +52,6 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -66,7 +65,6 @@ if USE_DCACHE_RAM action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -77,14 +75,12 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -94,23 +90,17 @@ else ldscript /cpu/x86/32bit/reset32.lds end -if USE_DCACHE_RAM mainboardinit cpu/amd/car/cache_as_ram.inc -end if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end -if USE_DCACHE_RAM if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end config chip.h diff --git a/src/mainboard/asus/m2v-mx_se/Config.lb b/src/mainboard/asus/m2v-mx_se/Config.lb index fec2300fde..8eac566e5e 100644 --- a/src/mainboard/asus/m2v-mx_se/Config.lb +++ b/src/mainboard/asus/m2v-mx_se/Config.lb @@ -55,7 +55,6 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -69,7 +68,6 @@ if USE_DCACHE_RAM action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -80,14 +78,12 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -97,23 +93,17 @@ else ldscript /cpu/x86/32bit/reset32.lds end -if USE_DCACHE_RAM mainboardinit cpu/amd/car/cache_as_ram.inc -end if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end -if USE_DCACHE_RAM if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end config chip.h diff --git a/src/mainboard/broadcom/blast/Config.lb b/src/mainboard/broadcom/blast/Config.lb index d77d099f4a..49c52f9418 100644 --- a/src/mainboard/broadcom/blast/Config.lb +++ b/src/mainboard/broadcom/blast/Config.lb @@ -50,8 +50,6 @@ end #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -70,14 +68,12 @@ if USE_DCACHE_RAM end -end ## ## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -85,7 +81,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -104,12 +99,10 @@ end mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -117,12 +110,7 @@ end ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM - ldscript /arch/i386/lib/failover.lds - else ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc - end end ### @@ -132,16 +120,12 @@ end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## diff --git a/src/mainboard/digitallogic/msm800sev/Config.lb b/src/mainboard/digitallogic/msm800sev/Config.lb index 0c5cfec0d7..c40445a34f 100644 --- a/src/mainboard/digitallogic/msm800sev/Config.lb +++ b/src/mainboard/digitallogic/msm800sev/Config.lb @@ -48,7 +48,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end -if USE_DCACHE_RAM #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -56,9 +55,6 @@ if USE_DCACHE_RAM action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end - - ## ## Build our 16 bit and 32 bit coreboot entry code @@ -107,10 +103,8 @@ end ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary Configuration files diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb index 73f4d6e5fb..6bc6505afc 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb +++ b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb @@ -82,7 +82,6 @@ object get_bus_conf.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -98,8 +97,6 @@ if USE_DCACHE_RAM end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -129,7 +126,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -137,8 +133,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) @@ -182,12 +176,10 @@ else end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -196,29 +188,22 @@ end ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end ## ## Include the secondary Configuration files diff --git a/src/mainboard/gigabyte/m57sli/Config.lb b/src/mainboard/gigabyte/m57sli/Config.lb index b8ca49fb6a..0a5f017b92 100644 --- a/src/mainboard/gigabyte/m57sli/Config.lb +++ b/src/mainboard/gigabyte/m57sli/Config.lb @@ -80,7 +80,6 @@ object get_bus_conf.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -96,8 +95,6 @@ if USE_DCACHE_RAM end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -127,7 +124,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -135,8 +131,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) @@ -180,12 +174,10 @@ else end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -194,15 +186,11 @@ end ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end @@ -213,14 +201,11 @@ end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end ## ## Include the secondary Configuration files diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Config.lb b/src/mainboard/iei/pcisa-lx-800-r10/Config.lb index 8ec000285f..7ff4556055 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/Config.lb +++ b/src/mainboard/iei/pcisa-lx-800-r10/Config.lb @@ -35,7 +35,6 @@ driver mainboard.o if HAVE_PIRQ_TABLE object irq_tables.o end -if USE_DCACHE_RAM # Compile cache_as_ram.c to auto.inc. makerule ./cache_as_ram_auto.inc # depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -44,7 +43,6 @@ if USE_DCACHE_RAM action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds @@ -63,10 +61,8 @@ if USE_FALLBACK_IMAGE # mainboardinit ./failover.inc end mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end dir /pc80 config chip.h diff --git a/src/mainboard/iwill/dk8_htx/Config.lb b/src/mainboard/iwill/dk8_htx/Config.lb index d9bed6ddd7..3bb42e86a5 100644 --- a/src/mainboard/iwill/dk8_htx/Config.lb +++ b/src/mainboard/iwill/dk8_htx/Config.lb @@ -129,8 +129,6 @@ if HAVE_ACPI_TABLES end end -if USE_DCACHE_RAM - if CONFIG_USE_INIT # compile cache_as_ram.c to auto.o makerule ./cache_as_ram_auto.o @@ -148,7 +146,6 @@ if USE_DCACHE_RAM end end -end if USE_FAILOVER_IMAGE else @@ -178,7 +175,6 @@ else end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -186,7 +182,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -215,12 +210,10 @@ end mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -229,15 +222,11 @@ end ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end @@ -248,16 +237,12 @@ end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## diff --git a/src/mainboard/lippert/roadrunner-lx/Config.lb b/src/mainboard/lippert/roadrunner-lx/Config.lb index 19dd58e091..182b482118 100644 --- a/src/mainboard/lippert/roadrunner-lx/Config.lb +++ b/src/mainboard/lippert/roadrunner-lx/Config.lb @@ -72,7 +72,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end -if USE_DCACHE_RAM # compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c" @@ -80,8 +79,6 @@ if USE_DCACHE_RAM action "perl -e 's/.rodata/.rom.data/g' -pi $@" action "perl -e 's/.text/.section .rom.text/g' -pi $@" end -end - ## ## Build our 16 bit and 32 bit coreboot entry code @@ -130,10 +127,8 @@ end ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary configuration files diff --git a/src/mainboard/lippert/spacerunner-lx/Config.lb b/src/mainboard/lippert/spacerunner-lx/Config.lb index 3e455f1470..243693de25 100644 --- a/src/mainboard/lippert/spacerunner-lx/Config.lb +++ b/src/mainboard/lippert/spacerunner-lx/Config.lb @@ -70,7 +70,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end -if USE_DCACHE_RAM # compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c" @@ -78,7 +77,6 @@ if USE_DCACHE_RAM action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end ## ## Build our 16 bit and 32 bit coreboot entry code @@ -127,10 +125,8 @@ end ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary configuration files diff --git a/src/mainboard/msi/ms7135/Config.lb b/src/mainboard/msi/ms7135/Config.lb index 1feec7fb63..a0174451cf 100644 --- a/src/mainboard/msi/ms7135/Config.lb +++ b/src/mainboard/msi/ms7135/Config.lb @@ -90,7 +90,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -104,7 +103,6 @@ if USE_DCACHE_RAM action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end ## ## Build our 16 bit and 32 bit coreboot entry code. @@ -123,12 +121,10 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (this is where coreboot is entered). @@ -151,12 +147,6 @@ else end end -if USE_DCACHE_RAM -else - ### Should this be in the northbridge code? - mainboardinit arch/i386/lib/cpu_reset.inc -end - ## ## Include an ID string (for safe flashing). ## @@ -178,13 +168,10 @@ else end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end - ### ### This is the early phase of coreboot startup. @@ -193,15 +180,11 @@ end ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end @@ -212,13 +195,11 @@ end ## ## Setup RAM ## -if USE_DCACHE_RAM if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -end ## ## Include the secondary configuration files diff --git a/src/mainboard/msi/ms7260/Config.lb b/src/mainboard/msi/ms7260/Config.lb index 992a424208..bdb9933d0a 100644 --- a/src/mainboard/msi/ms7260/Config.lb +++ b/src/mainboard/msi/ms7260/Config.lb @@ -54,7 +54,6 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -68,7 +67,6 @@ if USE_DCACHE_RAM action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end if USE_FAILOVER_IMAGE else @@ -95,14 +93,12 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -138,31 +134,23 @@ else end end -if USE_DCACHE_RAM mainboardinit cpu/amd/car/cache_as_ram.inc -end if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end -if USE_DCACHE_RAM if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end config chip.h diff --git a/src/mainboard/msi/ms9185/Config.lb b/src/mainboard/msi/ms9185/Config.lb index 99f8b77907..99a6ce5e97 100644 --- a/src/mainboard/msi/ms9185/Config.lb +++ b/src/mainboard/msi/ms9185/Config.lb @@ -77,8 +77,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end -if USE_DCACHE_RAM - if CONFIG_USE_INIT # compile cache_as_ram.c to auto.o makerule ./cache_as_ram_auto.o @@ -96,7 +94,6 @@ if USE_DCACHE_RAM end end -end ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -107,7 +104,6 @@ if USE_FALLBACK_IMAGE end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -115,7 +111,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -134,12 +129,10 @@ end mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -147,9 +140,7 @@ end ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end ### @@ -159,16 +150,12 @@ end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## diff --git a/src/mainboard/nvidia/l1_2pvv/Config.lb b/src/mainboard/nvidia/l1_2pvv/Config.lb index bb1b99b113..f838107e3f 100644 --- a/src/mainboard/nvidia/l1_2pvv/Config.lb +++ b/src/mainboard/nvidia/l1_2pvv/Config.lb @@ -111,8 +111,6 @@ if HAVE_ACPI_TABLES end end -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -127,8 +125,6 @@ if USE_DCACHE_RAM end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -158,7 +154,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -166,8 +161,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) @@ -211,12 +204,10 @@ else end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -225,29 +216,22 @@ end ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end ## ## Include the secondary Configuration files diff --git a/src/mainboard/pcengines/alix1c/Config.lb b/src/mainboard/pcengines/alix1c/Config.lb index 17c9933050..023d082629 100644 --- a/src/mainboard/pcengines/alix1c/Config.lb +++ b/src/mainboard/pcengines/alix1c/Config.lb @@ -68,7 +68,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end -if USE_DCACHE_RAM #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -76,9 +75,6 @@ if USE_DCACHE_RAM action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end - - ## ## Build our 16 bit and 32 bit coreboot entry code @@ -127,10 +123,8 @@ end ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary Configuration files diff --git a/src/mainboard/supermicro/h8dme/Config.lb b/src/mainboard/supermicro/h8dme/Config.lb index 616e582442..fc696b2546 100644 --- a/src/mainboard/supermicro/h8dme/Config.lb +++ b/src/mainboard/supermicro/h8dme/Config.lb @@ -77,7 +77,6 @@ object get_bus_conf.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./auto.o @@ -93,8 +92,6 @@ if USE_DCACHE_RAM end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -124,7 +121,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -132,8 +128,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) @@ -177,12 +171,10 @@ else end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -191,29 +183,22 @@ end ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -end ## ## Include the secondary Configuration files diff --git a/src/mainboard/supermicro/h8dmr/Config.lb b/src/mainboard/supermicro/h8dmr/Config.lb index ed0c1101f8..ea6abb65d5 100644 --- a/src/mainboard/supermicro/h8dmr/Config.lb +++ b/src/mainboard/supermicro/h8dmr/Config.lb @@ -80,7 +80,6 @@ object get_bus_conf.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./auto.o @@ -96,8 +95,6 @@ if USE_DCACHE_RAM end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -127,7 +124,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -135,8 +131,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) @@ -180,12 +174,10 @@ else end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -194,29 +186,22 @@ end ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -end ## ## Include the secondary Configuration files diff --git a/src/mainboard/technexion/tim8690/Config.lb b/src/mainboard/technexion/tim8690/Config.lb index 9e3ebe7fd4..47a41e6577 100644 --- a/src/mainboard/technexion/tim8690/Config.lb +++ b/src/mainboard/technexion/tim8690/Config.lb @@ -83,8 +83,6 @@ end #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -103,14 +101,12 @@ if USE_DCACHE_RAM end -end ## ## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -118,7 +114,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -137,12 +132,10 @@ end mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -150,12 +143,7 @@ end ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM - ldscript /arch/i386/lib/failover.lds - else ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc - end end ### @@ -165,16 +153,12 @@ end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## diff --git a/src/mainboard/tyan/s2912/Config.lb b/src/mainboard/tyan/s2912/Config.lb index 28adac4e92..b0cac7b0f4 100644 --- a/src/mainboard/tyan/s2912/Config.lb +++ b/src/mainboard/tyan/s2912/Config.lb @@ -81,8 +81,6 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -97,8 +95,6 @@ if USE_DCACHE_RAM end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -128,7 +124,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -136,8 +131,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) @@ -181,12 +174,10 @@ else end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -195,29 +186,22 @@ end ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end ## ## Include the secondary Configuration files diff --git a/src/mainboard/tyan/s2912_fam10/Config.lb b/src/mainboard/tyan/s2912_fam10/Config.lb index b9f1a5f3d8..b39e917b75 100644 --- a/src/mainboard/tyan/s2912_fam10/Config.lb +++ b/src/mainboard/tyan/s2912_fam10/Config.lb @@ -81,7 +81,6 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c if CONFIG_USE_INIT @@ -98,8 +97,6 @@ if USE_DCACHE_RAM end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -129,7 +126,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -137,8 +133,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) @@ -182,12 +176,10 @@ else end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -196,29 +188,22 @@ end ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end ## ## Include the secondary Configuration files |