diff options
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 7 |
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index ed09aaa936..e69369981d 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -238,6 +238,9 @@ struct soc_intel_tigerlake_config { */ uint16_t TcssAuxOri; + /* Connect Topology Command timeout value */ + uint16_t ITbtConnectTopologyTimeoutInMs; + /* * Override GPIO PM configuration: * 0: Use FSP default GPIO PM program, diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index bdcd357173..926d8eb7b4 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -114,6 +114,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) for (i = 0; i < 8; i++) params->IomTypeCPortPadCfg[i] = config->IomTypeCPortPadCfg[i]; + /* + * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will + * evaluate this UPD value and skip sending command. There will be no + * delay for command completion. + */ + params->ITbtConnectTopologyTimeoutInMs = 0; + /* Chipset Lockdown */ if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { params->PchLockDownGlobalSmi = 0; |