diff options
32 files changed, 43 insertions, 54 deletions
diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index cfab21956b..30d2cca87a 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -315,7 +315,7 @@ void lb_arch_add_records(struct lb_header *header) struct lb_tsc_info *tsc_info; /* Don't advertise a TSC rate unless it's constant. */ - if (!CONFIG(TSC_CONSTANT_RATE)) + if (!tsc_constant_rate()) return; freq_khz = tsc_freq_mhz() * 1000; diff --git a/src/arch/x86/timestamp.c b/src/arch/x86/timestamp.c index 92d9590af4..8cf0f96e31 100644 --- a/src/arch/x86/timestamp.c +++ b/src/arch/x86/timestamp.c @@ -22,7 +22,7 @@ uint64_t timestamp_get(void) int timestamp_tick_freq_mhz(void) { /* Chipsets that have a constant TSC provide this value correctly. */ - if (CONFIG(TSC_CONSTANT_RATE)) + if (tsc_constant_rate()) return tsc_freq_mhz(); /* Filling tick_freq_mhz = 0 in timestamps-table will trigger diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 77ba0bdb98..3e71469947 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -32,7 +32,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select TSC_MONOTONIC_TIMER - select TSC_CONSTANT_RATE select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select NO_SMM diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index db119a05cc..d8d8b97004 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -14,7 +14,6 @@ config CPU_SPECIFIC_OPTIONS select MMX select SSE2 select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 16bc03b076..564a428bbc 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -7,7 +7,6 @@ config CPU_INTEL_MODEL_1067X select SMP select SSE2 select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 43c4048786..1ba8894940 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -7,7 +7,6 @@ config CPU_INTEL_MODEL_106CX select SMP select SSE2 select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 572751186e..a76a95dc6d 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -12,7 +12,6 @@ config CPU_SPECIFIC_OPTIONS select SMP select SSE2 select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS select PARALLEL_CPU_INIT diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 97d8d3d0d6..8dae6ecc30 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS select MMX select SSE2 select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index ff16724651..3af52722f3 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -7,7 +7,6 @@ config CPU_INTEL_MODEL_6EX select SMP select SSE2 select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index e6c82564c9..cfd3e7c6e0 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -7,7 +7,6 @@ config CPU_INTEL_MODEL_6FX select SMP select SSE2 select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index d9324944da..3d0522a09d 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -25,6 +25,7 @@ config SLOT_SPECIFIC_OPTIONS # dummy select CPU_INTEL_MODEL_6XX select NO_SMM select NO_MONOTONIC_TIMER + select UNKNOWN_TSC_RATE config DCACHE_RAM_BASE hex diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 4ec46e0ac8..a2ebeb2325 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -9,7 +9,6 @@ config SOCKET_SPECIFIC_OPTIONS # dummy select MMX select SSE select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM select C_ENVIRONMENT_BOOTBLOCK diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index a6c9b74360..7504233bda 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -20,5 +20,6 @@ config CPU_QEMU_X86 select SMP select UDELAY_TSC select TSC_MONOTONIC_TIMER + select UNKNOWN_TSC_RATE select C_ENVIRONMENT_BOOTBLOCK select SMM_ASEG diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig index 4b96c7ce82..14acfd5662 100644 --- a/src/cpu/via/nano/Kconfig +++ b/src/cpu/via/nano/Kconfig @@ -25,6 +25,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select UDELAY_TSC select TSC_MONOTONIC_TIMER + select UNKNOWN_TSC_RATE select MMX select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index b316c1ffc3..85ebd831ea 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -34,12 +34,9 @@ config UDELAY_TSC bool default n -config TSC_CONSTANT_RATE - def_bool n - depends on UDELAY_TSC - help - This option asserts that the TSC ticks at a known constant rate. - Therefore, no TSC calibration is required. +config UNKNOWN_TSC_RATE + bool + default y if LAPIC_MONOTONIC_TIMER config TSC_MONOTONIC_TIMER def_bool n diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index ab7453f262..b3925b5051 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -1,6 +1,6 @@ bootblock-$(CONFIG_UDELAY_TSC) += delay_tsc.c ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c -romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c -verstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c -postcar-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c -smm-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c +romstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c +verstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c +postcar-$(CONFIG_UDELAY_TSC) += delay_tsc.c +smm-$(CONFIG_UDELAY_TSC) += delay_tsc.c diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index afcd1d1f7d..7aa887ae63 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -18,26 +18,9 @@ #include <delay.h> #include <thread.h> -static unsigned long clocks_per_usec CAR_GLOBAL; - -static unsigned long calibrate_tsc(void) -{ - if (CONFIG(TSC_CONSTANT_RATE)) - return tsc_freq_mhz(); - else - return calibrate_tsc_with_pit(); -} - void init_timer(void) { - if (!car_get_var(clocks_per_usec)) - car_set_var(clocks_per_usec, calibrate_tsc()); -} - -static inline unsigned long get_clocks_per_usec(void) -{ - init_timer(); - return car_get_var(clocks_per_usec); + (void)tsc_freq_mhz(); } void udelay(unsigned int us) @@ -51,7 +34,7 @@ void udelay(unsigned int us) start = rdtscll(); clocks = us; - clocks *= get_clocks_per_usec(); + clocks *= tsc_freq_mhz(); current = rdtscll(); while ((current - start) < clocks) { cpu_relax(); @@ -89,7 +72,7 @@ void timer_monotonic_get(struct mono_time *mt) current_tick = rdtscll(); ticks_elapsed = current_tick - mono_counter->last_value; - ticks_per_usec = get_clocks_per_usec(); + ticks_per_usec = tsc_freq_mhz(); /* Update current time and tick values only if a full tick occurred. */ if (ticks_elapsed >= ticks_per_usec) { diff --git a/src/drivers/pc80/pc/i8254.c b/src/drivers/pc80/pc/i8254.c index 8e15d4ded1..654f84a6d7 100644 --- a/src/drivers/pc80/pc/i8254.c +++ b/src/drivers/pc80/pc/i8254.c @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ +#include <arch/early_variables.h> #include <arch/io.h> #include <commonlib/helpers.h> #include <cpu/x86/tsc.h> @@ -122,3 +123,25 @@ unsigned long calibrate_tsc_with_pit(void) bad_ctc: return 0; } + +#if CONFIG(UNKNOWN_TSC_RATE) +static u32 g_timer_tsc CAR_GLOBAL; + +unsigned long tsc_freq_mhz(void) +{ + u32 tsc; + + tsc = car_get_var(g_timer_tsc); + if (tsc > 0) + return tsc; + + tsc = calibrate_tsc_with_pit(); + + /* Set some semi-ridiculous rate if approximation fails. */ + if (tsc == 0) + tsc = 5000; + + car_set_var(g_timer_tsc, tsc); + return tsc; +} +#endif diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index dd333e8930..c18f8782f0 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -63,4 +63,9 @@ static inline uint64_t tsc_to_uint64(tsc_t tstamp) /* Provided by CPU/chipset code for the TSC rate in MHz. */ unsigned long tsc_freq_mhz(void); +static inline int tsc_constant_rate(void) +{ + return !CONFIG(UNKNOWN_TSC_RATE); +} + #endif /* CPU_X86_TSC_H */ diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc index bbfe63b45a..247cc249bf 100644 --- a/src/northbridge/via/vx900/Makefile.inc +++ b/src/northbridge/via/vx900/Makefile.inc @@ -28,7 +28,6 @@ romstage-y += ./../../../southbridge/via/common/early_smbus_is_busy.c romstage-y += ./../../../southbridge/via/common/early_smbus_print_error.c romstage-y += ./../../../southbridge/via/common/early_smbus_reset.c romstage-y += ./../../../southbridge/via/common/early_smbus_wait_until_ready.c -romstage-y += ./../../../drivers/pc80/pc/udelay_io.c ramstage-y += pci_util.c ramstage-y += pcie.c diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index d87d634e6a..5f9792b28a 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -33,7 +33,6 @@ config CPU_SPECIFIC_OPTIONS select GENERIC_GPIO_LIB select IOAPIC select HAVE_USBDEBUG_OPTIONS - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select SOC_AMD_COMMON_BLOCK_SPI select TSC_SYNC_LFENCE diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index b54528f579..026f6da669 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -95,7 +95,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_CSE select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select PLATFORM_USES_FSP2_0 select UDK_2015_BINDING if !SOC_INTEL_GLK diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index c833c5360f..397e86768c 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -27,7 +27,6 @@ config CPU_SPECIFIC_OPTIONS select SMP select SPI_FLASH select SSE2 - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 5053790c75..7ea01863ae 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -34,7 +34,6 @@ config CPU_SPECIFIC_OPTIONS select SMP select SPI_FLASH select SSE2 - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 5856ef1e50..fadbb417ae 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -27,7 +27,6 @@ config CPU_SPECIFIC_OPTIONS select SMP select SPI_FLASH select SSE2 - select TSC_CONSTANT_RATE select TSC_SYNC_MFENCE select UDELAY_TSC select SOC_INTEL_COMMON diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 941c150892..3330a69081 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -102,7 +102,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_RESET select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_2017_BINDING diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 2aadcae584..cb3713d3b0 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -50,7 +50,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_PCR - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index efe12da480..5a8bec995b 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -36,7 +36,6 @@ config CPU_SPECIFIC_OPTIONS select SMP select SPI_FLASH select SSE2 - select TSC_CONSTANT_RATE select TSC_SYNC_MFENCE select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index 6c74a749a4..4c50828e0d 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -24,7 +24,6 @@ config CPU_SPECIFIC_OPTIONS select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select TSC_MONOTONIC_TIMER - select TSC_CONSTANT_RATE select HAVE_FSP_BIN select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SOC_INTEL_COMMON diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 993e9b2d3b..86f1ff53e0 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -53,7 +53,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_RESET select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_2017_BINDING diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index b752784d15..75f13543ca 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -34,7 +34,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_RESET select SOC_SETS_MSRS select SPI_FLASH - select TSC_CONSTANT_RATE select UART_OVERRIDE_REFCLK select UDELAY_TSC select UNCOMPRESSED_RAMSTAGE diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f9f6f9302b..d4720a21be 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -76,7 +76,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_RESET select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC |