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authorMichał Żygowski <michal.zygowski@3mdeb.com>2021-05-09 13:54:09 +0200
committerMichał Żygowski <michal.zygowski@3mdeb.com>2021-05-12 08:30:33 +0000
commitfb198c6b018d715a66096859ed089d0eef0cdf2d (patch)
tree8867a5b78cf638cd7c357660cc4c871cbca34f49 /util/chromeos/crosfirmware.sh
parentff7e2c86202084d4bbbdfd51a5b08331b8793364 (diff)
nb/amd/pi/00730F01: Use generic allocation functions for northbridge
Remove obsolete resource assigning functions. IO and MMIO address registers are currently set by amd_initcpuio to cover whole PCI hole under 4G to MMIO and IO 0x0000-0xFFFF is configured to be routed to southbridge already. Use generic PCI and resource allocation functions wherever possible to set northbridge resources. TEST=boot Debian with Linux 4.14 on apu2 4GB ECC and apu3 2GB no ECC Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I8dd5e40bce513c5ba7f1d42a06e7ab0846666942 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'util/chromeos/crosfirmware.sh')
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