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authorKarthikeyan Ramasubramanian <kramasub@google.com>2022-04-19 14:48:43 -0600
committerFelix Held <felix-coreboot@felixheld.de>2022-04-25 13:48:28 +0000
commit685f123852a5eee9dc93d861645e87394bbc30df (patch)
tree508c0dc0dd9505fabe4c16a7ce90422f2cd749f7 /util/archive
parent43f51a041d9f8ee5867031d043d541812b7fcab9 (diff)
soc/amd/sabrina: Modify start address of PSP verstage
PSP verstage can start at address 0 and use 200KB of PSP SRAM for execution. Modify both the PSP SRAM start address and size for use by PSP verstage. BUG=b:220848544 TEST=Build Skyrim BIOS image with PSP verstage enabled. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I73e13b82faa0f443570a0c839e7699a79bdae024 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
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