diff options
| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2022-04-19 14:48:43 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-25 13:48:28 +0000 |
| commit | 685f123852a5eee9dc93d861645e87394bbc30df (patch) | |
| tree | 508c0dc0dd9505fabe4c16a7ce90422f2cd749f7 | |
| parent | 43f51a041d9f8ee5867031d043d541812b7fcab9 (diff) | |
soc/amd/sabrina: Modify start address of PSP verstage
PSP verstage can start at address 0 and use 200KB of PSP SRAM for
execution. Modify both the PSP SRAM start address and size for use by
PSP verstage.
BUG=b:220848544
TEST=Build Skyrim BIOS image with PSP verstage enabled.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I73e13b82faa0f443570a0c839e7699a79bdae024
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
| -rw-r--r-- | src/soc/amd/sabrina/include/soc/psp_verstage_addr.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/amd/sabrina/include/soc/psp_verstage_addr.h b/src/soc/amd/sabrina/include/soc/psp_verstage_addr.h index 6636ea15e0..c8f07c9a57 100644 --- a/src/soc/amd/sabrina/include/soc/psp_verstage_addr.h +++ b/src/soc/amd/sabrina/include/soc/psp_verstage_addr.h @@ -6,12 +6,12 @@ #define AMD_SABRINA_PSP_VERSTAGE_ADDR_H /* - * Start of available space is 0x36000 and this is where the + * Start of available space is 0x0 and this is where the * header for the user app (verstage) must be mapped. - * Size is 0x14000 bytes + * Size is 208KB */ -#define PSP_SRAM_START 0x26000 -#define PSP_SRAM_SIZE (148K) +#define PSP_SRAM_START 0x0 +#define PSP_SRAM_SIZE (208K) #define VERSTAGE_START PSP_SRAM_START /* @@ -19,7 +19,7 @@ * and make the size a multiple of 4k */ -#define PSP_VERSTAGE_STACK_START 0x41000 +#define PSP_VERSTAGE_STACK_START 0x2a000 #define PSP_VERSTAGE_STACK_SIZE (40K) #endif /* AMD_SABRINA_PSP_VERSTAGE_ADDR_H */ |