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author | Subrata Banik <subratabanik@google.com> | 2024-03-16 18:06:02 +0530 |
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committer | Subrata Banik <subratabanik@google.com> | 2024-03-17 11:55:08 +0000 |
commit | 9355f318faceee026abc2dd7b57f8927df286ff7 (patch) | |
tree | 29198c189e93e5e196f9a42d2299effa5b5f97a8 /util/acpi/description.md | |
parent | a4c91e15f879eb2b6cf0984f97c6efdc6c8fdca8 (diff) |
soc/intel/cmn/ramtop: Refactor MTRR handling for RAMTOP range
This patch refactors RAMTOP MTRR type selection to address a critical
NEM logic bug on SoCs with non-power-of-two cache sets. This bug can
cause runtime hangs when Write Back (WB) caching is enabled.
Workaround: Force MTRR type to WC (Write Combining) on affected SoCs
when the cache set count is not a power of two.
BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified boot on google/ovis and google/rex (including Ovis with
non-power-of-two cache configuration).
Change-Id: Ia9a8f0d37d581b05c19ea7f9b1a07933caa956d4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81269
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/acpi/description.md')
0 files changed, 0 insertions, 0 deletions