soc/intel/apollolake: Clean up code by using common FAST_SPI module

This patch currently contains the following -
 1. Use SOC_INTEL_COMMON_BLOCK_FAST_SPI kconfig for common FAST_SPI code.
 2. Perform FAST_SPI programming by calling APIs from common FAST_SPI library.
 3. Use common FAST_SPI header file.

Change-Id: Ifd72734dadda541fe4c828e4f1716e532ec69c27
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/19080
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

8 files changed, 9 insertions, 540 deletions

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 852dfadaf0..d60f85eccf 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -54,6 +54,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_ACPI
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_BLOCK
+	select SOC_INTEL_COMMON_BLOCK_FAST_SPI
 	select SOC_INTEL_COMMON_BLOCK_ITSS
 	select SOC_INTEL_COMMON_BLOCK_LPSS
 	select SOC_INTEL_COMMON_BLOCK_PCR
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 1d5bac8ddb..36455f366f 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -11,7 +11,6 @@ subdirs-y += ../../../cpu/x86/cache
 bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/bootblock.c
 bootblock-y += car.c
-bootblock-y += flash_ctrlr.c
 bootblock-y += gpio.c
 bootblock-y += heci.c
 bootblock-y += lpc_lib.c
@@ -24,7 +23,6 @@ bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S
 
 romstage-y += car.c
 romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
-romstage-y += flash_ctrlr.c
 romstage-y += gpio.c
 romstage-y += heci.c
 romstage-y += i2c_early.c
@@ -38,7 +36,6 @@ romstage-y += pmutil.c
 romstage-y += reset.c
 romstage-y += spi.c
 
-smm-y += flash_ctrlr.c
 smm-y += mmap_boot.c
 smm-y += pmutil.c
 smm-y += gpio.c
@@ -52,7 +49,6 @@ ramstage-y += cpu.c
 ramstage-y += chip.c
 ramstage-y += cse.c
 ramstage-y += elog.c
-ramstage-y += flash_ctrlr.c
 ramstage-y += dsp.c
 ramstage-y += gpio.c
 ramstage-y += graphics.c
@@ -79,7 +75,6 @@ ramstage-y += xdci.c
 ramstage-y += xhci.c
 ramstage-y += sd.c
 
-postcar-y += flash_ctrlr.c
 postcar-y += memmap.c
 postcar-y += mmap_boot.c
 postcar-y += spi.c
@@ -89,7 +84,6 @@ postcar-y += tsc_freq.c
 postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
 
 verstage-y += car.c
-verstage-y += flash_ctrlr.c
 verstage-y += i2c_early.c
 verstage-y += heci.c
 verstage-y += memmap.c
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 8a56890af5..2c98be4fae 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -18,13 +18,13 @@
 #include <bootblock_common.h>
 #include <cpu/x86/mtrr.h>
 #include <device/pci.h>
+#include <intelblocks/fast_spi.h>
 #include <intelblocks/pcr.h>
-#include <intelblocks/systemagent.h>
 #include <intelblocks/rtc.h>
+#include <intelblocks/systemagent.h>
 #include <lib.h>
 #include <soc/iomap.h>
 #include <soc/cpu.h>
-#include <soc/flash_ctrlr.h>
 #include <soc/gpio.h>
 #include <soc/mmap_boot.h>
 #include <soc/systemagent.h>
@@ -92,35 +92,6 @@ static void cache_bios_region(void)
 	set_var_mtrr(mtrr, 4ULL*GiB - rom_size, rom_size, MTRR_TYPE_WRPROT);
 }
 
-/*
- * Program temporary BAR for SPI in case any of the stages before ramstage need
- * to access SPI MMIO regs. Ramstage will assign a new BAR during PCI
- * enumeration.
- */
-static void enable_spibar(void)
-{
-	device_t dev = PCH_DEV_SPI;
-	uint8_t val;
-
-	/* Disable Bus Master and MMIO space. */
-	val = pci_read_config8(dev, PCI_COMMAND);
-	val &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
-	pci_write_config8(dev, PCI_COMMAND, val);
-
-	/* Program Temporary BAR for SPI */
-	pci_write_config32(dev, PCI_BASE_ADDRESS_0,
-			   PRERAM_SPI_BASE_ADDRESS |
-			   PCI_BASE_ADDRESS_SPACE_MEMORY);
-
-	/* Enable Bus Master and MMIO Space */
-	val = pci_read_config8(dev, PCI_COMMAND);
-	val |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-	pci_write_config8(dev, PCI_COMMAND, val);
-
-	/* Initialize SPI to allow BIOS to write/erase on flash. */
-	spi_flash_init();
-}
-
 static void enable_pmcbar(void)
 {
 	device_t pmc = PCH_DEV_PMC;
@@ -152,7 +123,7 @@ void bootblock_soc_early_init(void)
 
 	enable_pm_timer_emulation();
 
-	enable_spibar();
+	fast_spi_early_init(PRERAM_SPI_BASE_ADDRESS);
 
 	cache_bios_region();
 
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 3108987329..5211f84383 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -24,6 +24,7 @@
 #include <cpu/x86/mp.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <intelblocks/fast_spi.h>
 #include <fsp/api.h>
 #include <fsp/util.h>
 #include <intelblocks/itss.h>
@@ -31,7 +32,6 @@
 #include <soc/iomap.h>
 #include <soc/itss.h>
 #include <soc/cpu.h>
-#include <soc/flash_ctrlr.h>
 #include <soc/intel/common/vbt.h>
 #include <soc/nvs.h>
 #include <soc/pci_devs.h>
@@ -578,7 +578,7 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase)
  */
 static void spi_flash_init_cb(void *unused)
 {
-	spi_flash_init();
+	fast_spi_init();
 }
 
 BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL);
diff --git a/src/soc/intel/apollolake/flash_ctrlr.c b/src/soc/intel/apollolake/flash_ctrlr.c
deleted file mode 100644
index 95f540cb18..0000000000
--- a/src/soc/intel/apollolake/flash_ctrlr.c
+++ /dev/null
@@ -1,391 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Intel Corp.
- * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#define __SIMPLE_DEVICE__
-
-#include <arch/early_variables.h>
-#include <arch/io.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <soc/flash_ctrlr.h>
-#include <soc/intel/common/spi_flash.h>
-#include <soc/pci_devs.h>
-#include <spi_flash.h>
-#include <spi-generic.h>
-#include <stdlib.h>
-#include <string.h>
-
-/* Helper to create a SPI context on API entry. */
-#define BOILERPLATE_CREATE_CTX(ctx)		\
-	struct spi_flash_ctx	real_ctx;	\
-	struct spi_flash_ctx *ctx = &real_ctx;	\
-	_get_spi_flash_ctx(ctx)
-
-/*
- * Anything that's not success is <0. Provided solely for readability, as these
- * constants are not used outside this file.
- */
-enum errors {
-	SUCCESS			= 0,
-	E_NOT_IMPLEMENTED	= -1,
-	E_TIMEOUT		= -2,
-	E_HW_ERROR		= -3,
-	E_ARGUMENT		= -4,
-};
-
-/* Reduce data-passing burden by grouping transaction data in a context. */
-struct spi_flash_ctx {
-	uintptr_t mmio_base;
-	device_t pci_dev;
-	uint32_t hsfsts_on_last_error;
-};
-
-static void _get_spi_flash_ctx(struct spi_flash_ctx *ctx)
-{
-	uint32_t bar;
-
-	/* FIXME: use device definition */
-	ctx->pci_dev = PCH_DEV_SPI;
-
-	bar = pci_read_config32(ctx->pci_dev, PCI_BASE_ADDRESS_0);
-	ctx->mmio_base = bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
-	ctx->hsfsts_on_last_error = 0;
-}
-
-/* Read register from the SPI flash controller. 'reg' is the register offset. */
-static uint32_t _spi_flash_ctrlr_reg_read(struct spi_flash_ctx *ctx,
-	uint16_t reg)
-{
-	uintptr_t addr =  ALIGN_DOWN(ctx->mmio_base + reg, 4);
-	return read32((void *)addr);
-}
-
-uint32_t spi_flash_ctrlr_reg_read(uint16_t reg)
-{
-	BOILERPLATE_CREATE_CTX(ctx);
-	return _spi_flash_ctrlr_reg_read(ctx, reg);
-}
-
-/* Write to register in SPI flash controller. 'reg' is the register offset. */
-static void _spi_flash_ctrlr_reg_write(struct spi_flash_ctx *ctx, uint16_t reg,
-				       uint32_t val)
-{
-	uintptr_t addr =  ALIGN_DOWN(ctx->mmio_base + reg, 4);
-	write32((void *)addr, val);
-
-}
-
-/*
- * The hardware datasheet is not clear on what HORD values actually do. It
- * seems that HORD_SFDP provides access to the first 8 bytes of the SFDP, which
- * is the signature and revision fields. HORD_JEDEC provides access to the
- * actual flash parameters, and is most likely what you want to use when
- * probing the flash from software.
- * It's okay to rely on SFPD, since the SPI flash controller requires an SFDP
- * 1.5 or newer compliant SPI flash chip.
- * NOTE: Due to the register layout of the hardware, all accesses will be
- * aligned to a 4 byte boundary.
- */
-static uint32_t read_spi_flash_sfdp_param(struct spi_flash_ctx *ctx,
-					  uint16_t sfdp_reg)
-{
-	uint32_t ptinx_index = sfdp_reg & SPIBAR_PTINX_IDX_MASK;
-	_spi_flash_ctrlr_reg_write(ctx, SPIBAR_PTINX,
-				   ptinx_index | SPIBAR_PTINX_HORD_JEDEC);
-	return _spi_flash_ctrlr_reg_read(ctx, SPIBAR_PTDATA);
-}
-
-/* Fill FDATAn FIFO in preparation for a write transaction. */
-static void fill_xfer_fifo(struct spi_flash_ctx *ctx, const void *data,
-			   size_t len)
-{
-	len = min(len, SPIBAR_FDATA_FIFO_SIZE);
-
-	/* YES! memcpy() works. FDATAn does not require 32-bit accesses. */
-	memcpy((void *)(ctx->mmio_base + SPIBAR_FDATA(0)), data, len);
-}
-
-/* Drain FDATAn FIFO after a read transaction populates data. */
-static void drain_xfer_fifo(struct spi_flash_ctx *ctx, void *dest, size_t len)
-{
-	len = min(len, SPIBAR_FDATA_FIFO_SIZE);
-
-	/* YES! memcpy() works. FDATAn does not require 32-bit accesses. */
-	memcpy(dest, (void *)(ctx->mmio_base + SPIBAR_FDATA(0)), len);
-}
-
-/* Fire up a transfer using the hardware sequencer. */
-static void start_hwseq_xfer(struct spi_flash_ctx *ctx, uint32_t hsfsts_cycle,
-				 uint32_t flash_addr, size_t len)
-{
-	/* Make sure all W1C status bits get cleared. */
-	uint32_t hsfsts = SPIBAR_HSFSTS_W1C_BITS;
-	/* Set up transaction parameters. */
-	hsfsts |= hsfsts_cycle & SPIBAR_HSFSTS_FCYCLE_MASK;
-	hsfsts |= SPIBAR_HSFSTS_FBDC(len - 1);
-
-	_spi_flash_ctrlr_reg_write(ctx, SPIBAR_FADDR, flash_addr);
-	_spi_flash_ctrlr_reg_write(ctx, SPIBAR_HSFSTS_CTL,
-			     hsfsts | SPIBAR_HSFSTS_FGO);
-}
-
-static void print_xfer_error(struct spi_flash_ctx *ctx,
-			     const char *failure_reason, uint32_t flash_addr)
-{
-	printk(BIOS_ERR, "SPI Transaction %s at flash offset %x.\n"
-			 "\tHSFSTS = 0x%08x\n",
-	       failure_reason, flash_addr, ctx->hsfsts_on_last_error);
-}
-
-static int wait_for_hwseq_xfer(struct spi_flash_ctx *ctx)
-{
-	uint32_t hsfsts;
-	do {
-		hsfsts = _spi_flash_ctrlr_reg_read(ctx, SPIBAR_HSFSTS_CTL);
-
-		if (hsfsts & SPIBAR_HSFSTS_FCERR) {
-			ctx->hsfsts_on_last_error = hsfsts;
-			return E_HW_ERROR;
-		}
-	/* TODO: set up timer and abort on timeout */
-	} while (!(hsfsts & SPIBAR_HSFSTS_FDONE));
-
-	return SUCCESS;
-}
-
-/* Execute SPI flash transfer. This is a blocking call. */
-static int exec_sync_hwseq_xfer(struct spi_flash_ctx *ctx,
-				uint32_t hsfsts_cycle, uint32_t flash_addr,
-				size_t len)
-{
-	int ret;
-	start_hwseq_xfer(ctx, hsfsts_cycle, flash_addr, len);
-	ret = wait_for_hwseq_xfer(ctx);
-	if (ret != SUCCESS) {
-		const char *reason = (ret == E_TIMEOUT) ? "timeout" : "error";
-		print_xfer_error(ctx, reason, flash_addr);
-	}
-	return ret;
-}
-
-unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
-{
-	return MIN(buf_len, SPIBAR_FDATA_FIFO_SIZE);
-}
-
-/*
- * Write-protection status for BIOS region (BIOS_CONTROL register):
- * EISS/WPD bits	00	01	10	11
- *			--	--	--	--
- * normal mode		RO	RW	RO	RO
- * SMM mode		RO	RW	RO	RW
- */
-void spi_flash_init(void)
-{
-	uint32_t bios_ctl;
-
-	BOILERPLATE_CREATE_CTX(ctx);
-
-	bios_ctl = pci_read_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL);
-	bios_ctl |= SPIBAR_BIOS_CONTROL_WPD;
-	bios_ctl &= ~SPIBAR_BIOS_CONTROL_EISS;
-
-	/* Enable Prefetching and caching. */
-	bios_ctl |= SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE;
-	bios_ctl &= ~SPIBAR_BIOS_CONTROL_CACHE_DISABLE;
-
-	pci_write_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL, bios_ctl);
-}
-
-/* Flash device operations. */
-static struct spi_flash boot_flash CAR_GLOBAL;
-
-static int nuclear_spi_flash_erase(const struct spi_flash *flash,
-				uint32_t offset, size_t len)
-{
-	int ret;
-	size_t erase_size;
-	uint32_t erase_cycle;
-
-	BOILERPLATE_CREATE_CTX(ctx);
-
-	if (!IS_ALIGNED(offset, 4 * KiB) || !IS_ALIGNED(len, 4 * KiB)) {
-		printk(BIOS_ERR, "BUG! SPI erase region not sector aligned.\n");
-		return E_ARGUMENT;
-	}
-
-	while (len) {
-		if (IS_ALIGNED(offset, 64 * KiB) && (len >= 64 * KiB)) {
-			erase_size = 64 * KiB;
-			erase_cycle = SPIBAR_HSFSTS_CYCLE_64K_ERASE;
-		} else {
-			erase_size = 4 * KiB;
-			erase_cycle = SPIBAR_HSFSTS_CYCLE_4K_ERASE;
-		}
-		printk(BIOS_SPEW, "Erasing flash addr %x + %zu KiB\n",
-		       offset, erase_size / KiB);
-
-		ret = exec_sync_hwseq_xfer(ctx, erase_cycle, offset, 0);
-		if (ret != SUCCESS)
-			return ret;
-
-		offset += erase_size;
-		len -= erase_size;
-	}
-
-	return SUCCESS;
-}
-
-/*
- * Ensure read/write xfer len is not greater than SPIBAR_FDATA_FIFO_SIZE and
- * that the operation does not cross 256-byte boundary.
- */
-static size_t get_xfer_len(uint32_t addr, size_t len)
-{
-	size_t xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE);
-	size_t bytes_left = ALIGN_UP(addr, 256) - addr;
-
-	if (bytes_left)
-		xfer_len = min(xfer_len, bytes_left);
-
-	return xfer_len;
-}
-
-static int nuclear_spi_flash_read(const struct spi_flash *flash, uint32_t addr,
-				size_t len, void *buf)
-{
-	int ret;
-	size_t xfer_len;
-	uint8_t *data = buf;
-
-	BOILERPLATE_CREATE_CTX(ctx);
-
-	while (len) {
-		xfer_len = get_xfer_len(addr, len);
-
-		ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_READ,
-						addr, xfer_len);
-		if (ret != SUCCESS)
-			return ret;
-
-		drain_xfer_fifo(ctx, data, xfer_len);
-
-		addr += xfer_len;
-		data += xfer_len;
-		len -= xfer_len;
-	}
-
-	return SUCCESS;
-}
-
-static int nuclear_spi_flash_write(const struct spi_flash *flash, uint32_t addr,
-				size_t len, const void *buf)
-{
-	int ret;
-	size_t xfer_len;
-	const uint8_t *data = buf;
-
-	BOILERPLATE_CREATE_CTX(ctx);
-
-	while (len) {
-		xfer_len = get_xfer_len(addr, len);
-		fill_xfer_fifo(ctx, data, xfer_len);
-
-		ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_WRITE,
-						addr, xfer_len);
-		if (ret != SUCCESS)
-			return ret;
-
-		addr += xfer_len;
-		data += xfer_len;
-		len -= xfer_len;
-	}
-
-	return SUCCESS;
-}
-
-static int nuclear_spi_flash_status(const struct spi_flash *flash, uint8_t *reg)
-{
-	int ret;
-	BOILERPLATE_CREATE_CTX(ctx);
-
-	ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_RD_STATUS, 0,
-				   sizeof(*reg));
-	if (ret != SUCCESS)
-		return ret;
-
-	drain_xfer_fifo(ctx, reg, sizeof(*reg));
-	return ret;
-}
-
-/*
- * We can't use FDOC and FDOD to read FLCOMP, as previous platforms did.
- * For details see:
- * Ch 31, SPI: p. 194
- * The size of the flash component is always taken from density field in the
- * SFDP table. FLCOMP.C0DEN is no longer used by the Flash Controller.
- */
-struct spi_flash *spi_flash_programmer_probe(struct spi_slave *dev, int force)
-{
-	BOILERPLATE_CREATE_CTX(ctx);
-	struct spi_flash *flash;
-	uint32_t flash_bits;
-
-	flash = car_get_var_ptr(&boot_flash);
-
-	/*
-	 * bytes = (bits + 1) / 8;
-	 * But we need to do the addition in a way which doesn't overflow for
-	 * 4 Gbit devices (flash_bits == 0xffffffff).
-	 */
-	/* FIXME: Don't hardcode 0x04 ? */
-	flash_bits = read_spi_flash_sfdp_param(ctx, 0x04);
-	flash->size = (flash_bits >> 3) + 1;
-
-	memcpy(&flash->spi, dev, sizeof(*dev));
-	flash->name = "Apollolake hardware sequencer";
-
-	/* Can erase both 4 KiB and 64 KiB chunks. Declare the smaller size. */
-	flash->sector_size = 4 * KiB;
-	/*
-	 * FIXME: Get erase+cmd, and status_cmd from SFDP.
-	 *
-	 * flash->erase_cmd = ???
-	 * flash->status_cmd = ???
-	 */
-
-	flash->internal_write = nuclear_spi_flash_write;
-	flash->internal_erase = nuclear_spi_flash_erase;
-	flash->internal_read = nuclear_spi_flash_read;
-	flash->internal_status = nuclear_spi_flash_status;
-
-	return flash;
-}
-
-int spi_flash_get_fpr_info(struct fpr_info *info)
-{
-	BOILERPLATE_CREATE_CTX(ctx);
-
-	if (!ctx->mmio_base)
-		return -1;
-
-	info->base = ctx->mmio_base + SPIBAR_FPR_BASE;
-	info->max = SPIBAR_FPR_MAX;
-
-	return 0;
-}
diff --git a/src/soc/intel/apollolake/include/soc/flash_ctrlr.h b/src/soc/intel/apollolake/include/soc/flash_ctrlr.h
deleted file mode 100644
index 336ce5266f..0000000000
--- a/src/soc/intel/apollolake/include/soc/flash_ctrlr.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_APOLLOLAKE_SPI_H_
-#define _SOC_APOLLOLAKE_SPI_H_
-
-/* PCI configuration registers */
-#define SPIBAR_BIOS_CONTROL		0xdc
-/* Bit definitions for BIOS_CONTROL */
-#define  SPIBAR_BIOS_CONTROL_WPD		(1 << 0)
-#define  SPIBAR_BIOS_CONTROL_CACHE_DISABLE	(1 << 2)
-#define  SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE	(1 << 3)
-#define  SPIBAR_BIOS_CONTROL_EISS		(1 << 5)
-
-/* Maximum bytes of data that can fit in FDATAn registers */
-#define SPIBAR_FDATA_FIFO_SIZE		0x40
-
-/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */
-#define SPIBAR_BIOS_BFPREG		0x00
-#define SPIBAR_HSFSTS_CTL		0x04
-#define SPIBAR_FADDR			0x08
-#define SPIBAR_FDATA(n)			(0x10 + ((n) & 0xf) * 4)
-#define SPIBAR_FPR_BASE			0x84
-#define SPIBAR_PTINX			0xcc
-#define SPIBAR_PTDATA			0xd0
-
-#define SPIBAR_FPR_MAX			5
-
-/* Bit definitions and masks for BIOS_BFPREG register. */
-#define  SPIBAR_BFPREG_PRB_MASK	(0x7fff)
-#define  SPIBAR_BFPREG_PRL_SHIFT	(16)
-#define  SPIBAR_BFPREG_PRL_MASK	(0x7fff << SPIBAR_BFPREG_PRL_SHIFT)
-#define  SPIBAR_BFPREG_SBRS		(1 << 31)
-
-/* Bit definitions for HSFSTS_CTL register */
-#define  SPIBAR_HSFSTS_FBDC_MASK	(0x3f << 24)
-#define  SPIBAR_HSFSTS_FBDC(n)		(((n) << 24) & SPIBAR_HSFSTS_FBDC_MASK)
-#define  SPIBAR_HSFSTS_WET		(1 << 21)
-#define  SPIBAR_HSFSTS_FCYCLE_MASK	(0xf << 17)
-#define  SPIBAR_HSFSTS_FCYCLE(cyc)	(((cyc) << 17) \
-					& SPIBAR_HSFSTS_FCYCLE_MASK)
-#define  SPIBAR_HSFSTS_FGO		(1 << 16)
-#define  SPIBAR_HSFSTS_FLOCKDN		(1 << 15)
-#define  SPIBAR_HSFSTS_FDV		(1 << 14)
-#define  SPIBAR_HSFSTS_FDOPSS		(1 << 13)
-#define  SPIBAR_HSFSTS_SAF_CE		(1 << 8)
-#define  SPIBAR_HSFSTS_SAF_ACTIVE	(1 << 7)
-#define  SPIBAR_HSFSTS_SAF_LE		(1 << 6)
-#define  SPIBAR_HSFSTS_SCIP		(1 << 5)
-#define  SPIBAR_HSFSTS_SAF_DLE		(1 << 4)
-#define  SPIBAR_HSFSTS_SAF_ERROR	(1 << 3)
-#define  SPIBAR_HSFSTS_AEL		(1 << 2)
-#define  SPIBAR_HSFSTS_FCERR		(1 << 1)
-#define  SPIBAR_HSFSTS_FDONE		(1 << 0)
-#define  SPIBAR_HSFSTS_W1C_BITS	(0xff)
-/* Supported flash cycle types */
-#define  SPIBAR_HSFSTS_CYCLE_READ	SPIBAR_HSFSTS_FCYCLE(0)
-#define  SPIBAR_HSFSTS_CYCLE_WRITE	SPIBAR_HSFSTS_FCYCLE(2)
-#define  SPIBAR_HSFSTS_CYCLE_4K_ERASE	SPIBAR_HSFSTS_FCYCLE(3)
-#define  SPIBAR_HSFSTS_CYCLE_64K_ERASE	SPIBAR_HSFSTS_FCYCLE(4)
-#define  SPIBAR_HSFSTS_CYCLE_RD_STATUS	SPIBAR_HSFSTS_FCYCLE(8)
-
-/* Bit definitions for PTINX register */
-#define  SPIBAR_PTINX_COMP_0		(0 << 14)
-#define  SPIBAR_PTINX_COMP_1		(1 << 14)
-#define  SPIBAR_PTINX_HORD_SFDP		(0 << 12)
-#define  SPIBAR_PTINX_HORD_PARAM	(1 << 12)
-#define  SPIBAR_PTINX_HORD_JEDEC	(2 << 12)
-#define  SPIBAR_PTINX_IDX_MASK		0xffc
-
-/*
- * Reads status register. On success returns 0 and status contains the value
- * read from the status register. On error returns -1.
- */
-int spi_flash_read_status(uint8_t *status);
-
-/* Read SPI controller register. */
-uint32_t spi_flash_ctrlr_reg_read(uint16_t reg);
-
-void spi_flash_init(void);
-#endif
diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c
index 50d0ff0590..598c068428 100644
--- a/src/soc/intel/apollolake/mmap_boot.c
+++ b/src/soc/intel/apollolake/mmap_boot.c
@@ -22,7 +22,7 @@
 #include <commonlib/region.h>
 #include <console/console.h>
 #include <fmap.h>
-#include <soc/flash_ctrlr.h>
+#include <intelblocks/fast_spi.h>
 #include <soc/mmap_boot.h>
 
 /*
@@ -65,7 +65,7 @@ static struct xlate_region_device real_dev CAR_GLOBAL;
 
 static void bios_mmap_init(void)
 {
-	size_t size, start, bios_end, bios_mapped_size;
+	size_t size, start, bios_mapped_size;
 	uintptr_t base;
 
 	size = car_get_var(bios_size);
@@ -73,18 +73,7 @@ static void bios_mmap_init(void)
 	/* If bios_size is initialized, then bail out. */
 	if (size != 0)
 		return;
-
-	/*
-	 * BIOS_BFPREG provides info about BIOS Flash Primary Region
-	 * Base and Limit.
-	 * Base and Limit fields are in units of 4KiB.
-	 */
-	uint32_t val = spi_flash_ctrlr_reg_read(SPIBAR_BIOS_BFPREG);
-
-	start = (val & SPIBAR_BFPREG_PRB_MASK) * 4 * KiB;
-	bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >>
-		     SPIBAR_BFPREG_PRL_SHIFT) + 1) * 4 * KiB;
-	size = bios_end - start;
+	start = fast_spi_get_bios_region(&size);
 
 	/* BIOS region is mapped right below 4G. */
 	base = 4ULL * GiB - size;
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index c1353c8240..98c70156da 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -33,7 +33,6 @@
 #include <fsp/util.h>
 #include <reset.h>
 #include <soc/cpu.h>
-#include <soc/flash_ctrlr.h>
 #include <soc/intel/common/mrc_cache.h>
 #include <soc/iomap.h>
 #include <soc/systemagent.h>