diff options
author | Chris Wang <chris.wang@amd.corp-partner.google.com> | 2021-04-28 00:03:03 +0800 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-30 16:18:27 +0000 |
commit | ca084b8db29ebf0eed63e5204213a15a6c8b3f53 (patch) | |
tree | cc8c45b978eef17c6d48ca00fd8745b61e3aa2e1 /src | |
parent | 66e35fb34132895ef1375268e19aa550af4e421b (diff) |
mb/google/mancomb: Add STAPM values to overridetree
Follow the FP6 IRM(#56328) to set the stapm parameter
and allow other mancomb variants boards can customize those parameters.
BUG=b:1181157669
TEST=build.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ib3ed76e5212a5a8b5fb4fcc3d6884ceff82377b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src')
-rw-r--r-- | src/mainboard/google/mancomb/variants/baseboard/devicetree.cb | 2 | ||||
-rw-r--r-- | src/mainboard/google/mancomb/variants/mancomb/overridetree.cb | 8 |
2 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb index 9bf52c7fa1..ab5ade728c 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip soc/amd/cezanne + register "system_configuration" = "3" + # eSPI Configuration register "common_config.espi_config" = "{ .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, diff --git a/src/mainboard/google/mancomb/variants/mancomb/overridetree.cb b/src/mainboard/google/mancomb/variants/mancomb/overridetree.cb index 891b4ebf0b..ef52ac0788 100644 --- a/src/mainboard/google/mancomb/variants/mancomb/overridetree.cb +++ b/src/mainboard/google/mancomb/variants/mancomb/overridetree.cb @@ -1,4 +1,12 @@ chip soc/amd/cezanne + + register "slow_ppt_limit_mW" = "37500" + register "fast_ppt_limit_mW" = "48000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "275" + register "sustained_power_limit_mW" = "25000" + register "thermctl_limit_degreeC" = "100" + device domain 0 on end # domain |