diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2023-04-24 17:29:36 -0700 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2023-07-13 01:05:35 +0000 |
| commit | 7d1a037f881f08969e47c197023f53b39ab7a6a6 (patch) | |
| tree | 79131d24596d9a48401c076162637a0fe82a97f6 /src | |
| parent | 6a6550be4f80296210893c05d83b0545e8567c2d (diff) | |
soc/intel/alderlake: Hook up UPD DisableSagvReorder
Hook the newly exposed DisableSagvReorder UPD up so that
boards can configure is via devicetree.
BUG=b:268546941
TEST=Verified by enabling/disabling the UPD on google/brya
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I89235d9384b67f03e68425aadd3458e1c77ff555
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 7 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/romstage/fsp_params.c | 1 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index f4cab6fe6a..591d8be52f 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -737,6 +737,13 @@ struct soc_intel_alderlake_config { * Set this to 1 in order to reduce BasicMemoryTest size */ bool lower_basic_mem_test_size; + + /* + * Enable or Disable SaGV reordering operation. + * Default is set to 0, SaGV reordering enabled. + * Set this to 1 in order to disable SaGV reordering. + */ + bool disable_sagv_reorder; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 1326cb5c1a..6b701edd20 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -160,6 +160,7 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, } #if CONFIG(SOC_INTEL_RAPTORLAKE) m_cfg->LowerBasicMemTestSize = config->lower_basic_mem_test_size; + m_cfg->DisableSagvReorder = config->disable_sagv_reorder; #endif } |