diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-05-05 13:32:36 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-06 23:31:19 +0000 |
| commit | 6eced03b25954e370e20e62f2cbe41f9d5626eae (patch) | |
| tree | 988dfae40b74089e59617bcba7f79d64d632543a /src | |
| parent | d2d762a4c96587a8197a8e11706bda24e7a2200f (diff) | |
soc/amd/common/espi: Don't set alert pin in espi_set_initial_config
The eSPI spec says that the Alert Mode defaults to in-band on reset.
This change ensures the controller is in sync with the eSPI peripheral.
The configured alert mode is configured in
espi_set_general_configuration.
BUG=b:187122344, b:186135022
TEST=Boot guybrush and make sure we don't get any eSPI errors.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib43e190d08d77ecfcd22ead2bf42e5de2202b555
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52953
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/common/block/lpc/espi_util.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index ade1aaa60f..519130a653 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -864,9 +864,6 @@ static void espi_set_initial_config(const struct espi_config *mb_cfg) { uint32_t espi_initial_mode = ESPI_OP_FREQ_16_MHZ | ESPI_IO_MODE_SINGLE; - if (mb_cfg->dedicated_alert_pin) - espi_initial_mode |= ESPI_ALERT_MODE; - espi_write32(ESPI_SLAVE0_CONFIG, espi_initial_mode); } |