diff options
| author | Marc Jones <marcjones@sysproconsulting.com> | 2021-03-02 15:16:25 -0700 |
|---|---|---|
| committer | Marc Jones <marc@marcjonesconsulting.com> | 2021-03-09 16:51:13 +0000 |
| commit | 6545145f0d3cda84c0dc8a01db6ce03f6dd87832 (patch) | |
| tree | e46681a5b1919ea9db6948ba5960cca97d43a36e /src | |
| parent | 81ef9c21da5e794db63ed174f334669c8c3cbd56 (diff) | |
soc/intel/xeon_sp: Set SMI lock
Prevent writes to Global SMI enable as recommended by the BWG.
Change-Id: I7824464e53a2ca1e860c1aa40d8a7d26e948c418
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/xeon_sp/lockdown.c | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/src/soc/intel/xeon_sp/lockdown.c b/src/soc/intel/xeon_sp/lockdown.c index 2fa53c92b3..0e21680e95 100644 --- a/src/soc/intel/xeon_sp/lockdown.c +++ b/src/soc/intel/xeon_sp/lockdown.c @@ -16,7 +16,19 @@ static void lpc_lockdown_config(int chipset_lockdown) } } -static void pmc_lockdown_config(void) +static void pmc_lock_smi(void) +{ + uint8_t *pmcbase; + uint8_t reg8; + + pmcbase = pmc_mmio_regs(); + + reg8 = read8(pmcbase + GEN_PMCON_A); + reg8 |= SMI_LOCK; + write8(pmcbase + GEN_PMCON_A, reg8); +} + +static void pmc_lockdown_config(int chipset_lockdown) { uint8_t *pmcbase; u32 pmsyncreg; @@ -29,6 +41,9 @@ static void pmc_lockdown_config(void) /* Make sure payload/OS can't trigger global reset */ pmc_global_reset_disable_and_lock(); + + if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) + pmc_lock_smi(); } void soc_lockdown_config(int chipset_lockdown) @@ -37,5 +52,5 @@ void soc_lockdown_config(int chipset_lockdown) lpc_lockdown_config(chipset_lockdown); /* PMC lock down configuration */ - pmc_lockdown_config(); + pmc_lockdown_config(chipset_lockdown); } |