diff options
| -rw-r--r-- | src/soc/intel/xeon_sp/lockdown.c | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/src/soc/intel/xeon_sp/lockdown.c b/src/soc/intel/xeon_sp/lockdown.c index 2fa53c92b3..0e21680e95 100644 --- a/src/soc/intel/xeon_sp/lockdown.c +++ b/src/soc/intel/xeon_sp/lockdown.c @@ -16,7 +16,19 @@ static void lpc_lockdown_config(int chipset_lockdown) } } -static void pmc_lockdown_config(void) +static void pmc_lock_smi(void) +{ + uint8_t *pmcbase; + uint8_t reg8; + + pmcbase = pmc_mmio_regs(); + + reg8 = read8(pmcbase + GEN_PMCON_A); + reg8 |= SMI_LOCK; + write8(pmcbase + GEN_PMCON_A, reg8); +} + +static void pmc_lockdown_config(int chipset_lockdown) { uint8_t *pmcbase; u32 pmsyncreg; @@ -29,6 +41,9 @@ static void pmc_lockdown_config(void) /* Make sure payload/OS can't trigger global reset */ pmc_global_reset_disable_and_lock(); + + if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) + pmc_lock_smi(); } void soc_lockdown_config(int chipset_lockdown) @@ -37,5 +52,5 @@ void soc_lockdown_config(int chipset_lockdown) lpc_lockdown_config(chipset_lockdown); /* PMC lock down configuration */ - pmc_lockdown_config(); + pmc_lockdown_config(chipset_lockdown); } |